Daniel Beeker

As SoCs move toward heterogeneous architectures and chiplets, programmable logic is no longer just a prototyping tool—it’s becoming a design-time decision. In this blog, QuickLogic breaks down the practical differences between FPGAs and embedded FPGAs (eFPGAs) from an implementation perspective: When a standalone FPGA makes sense for iteration, standards evolution, and field updates - Why eFPGAs integrated into an ASIC/SoC can deliver lower latency, better power efficiency, and smaller footprint - How on-die reconfigurable logic enables post-silicon flexibility without the cost and risk of a full respin - Architectural and system-level considerations engineers should weigh early in the design cycle If you’re designing custom silicon and thinking about how to preserve flexibility without sacrificing PPA, this is a useful comparison. 👉 Read blog at: https://lnkd.in/gQZjDH99 #FPGA #eFPGA #SoCDesign #ASIC #ChipArchitecture #SemiconductorEngineering #QuickLogic

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Anyone who has tried to program or debug multiple FPGA or embedded boards over JTAG knows that the problem is rarely JTAG itself it’s everything built around it. Proprietary multi-drop setups, expensive debug probes, and poor scalability quickly become bottlenecks as soon as a project moves beyond a single board. Toolchains don’t always cooperate, and scaling up often leads to a frustrating question: “Do I really need to buy more hardware just to debug more targets?” That frustration is exactly what led us to build Periplex JTAG. Periplex JTAG is a software solution, designed to let engineers program and debug multiple embedded systems using a single Vaaman board. It uses the Periplex expansion architecture to manage multiple JTAG targets, while integrating directly with OpenOCD, so engineers can stay within familiar, scriptable workflows. By moving the complexity into software, Periplex JTAG reduces the need for multiple physical probes, lowers cost, and makes JTAG scale naturally in lab, startup, and research environments. This approach has already been tested with STM32, ESP32, and Trion & Titanium FPGAs, and continues to evolve based on real-world engineering feedback. The goal is not to replace existing tools, but to make them scale better without adding more hardware to the bench.

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Designing modern PCBs means working with faster signals, tighter margins, and greater complexity. It’s no surprise that many engineers struggle to maintain signal integrity control, especially when issues only become apparent after prototyping. That’s where the Signal Analyzer by Keysight Technologies comes in. Built right into Altium Designer, this powerful extension helps you catch potential problems early and design with greater confidence without switching tools or slowing down your workflow. Our FREE whitepaper shows you how it works and why it can make a big difference - even if you’re not a signal integrity expert. Download the whitepaper here: https://bit.ly/3EQnDc0 Take the stress out of your next PCB design! #AltiumDesigner #SignalAnalyzer #PCBDesign #SignalIntegrity #Keysight

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Understanding narrowband emissions creation by RS422. It is necessary to pay attention to details in order to pass some standards. This article discusses what can happen if you route an RS422 or RS485 trace incorrectly. https://lnkd.in/ePgm9sNY #emc

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Nothing hurts more than doing everything right in a hardware design, only for your board to fail because of a single footprint. This article will help you avoid this pitfall by explaining how to manage ECAD libraries for consistent PCB layout design. Learn more: https://bit.ly/4psh2WH #Altium #ECAD #PCBLayout #ElectronicsDesign #PCBDesign

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📣Calling all beginner chip designers! Are you considering chiplet-based approaches? https://bit.ly/3HV4kj3 Our latest blog post outlines eight best practices for #multidie designs. Give it a read at the link above and let us know what you think in the comments.

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Qorvo has released three new PC-based IoT development calculators to help engineers optimize crystal selection, battery life and RF link performance. These tools—Crystal Procurement Tool, Energy Budget Calculator and Link Budget & Range Calculator—streamline critical design decisions for faster, more reliable product development. https://ow.ly/VGCT50Wptrv #IoTDevelopment #RFLinkPerformance #BatteryLife

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High-density interconnect (HDI) is where routing, signal integrity and manufacturing all collide. Yet many boards fail because designers still use standard via types, loose constraints and "we'll fit it later" routing. 👉 https://ow.ly/OnLO50XuUHZ This blog walks through how OrCAD X gives you the tools to manage microvias, buried & blind via stacks, impedance constraints and routing zones so your next HDI layout isn't a gamble. #HDI #PCBDesign #OrCADX #SignalIntegrity

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More Data, More Redundant Interconnects https://lnkd.in/gGz-Np4u Circuits are being pushed harder and longer, particularly with AI, speeding up the aging of data paths. Photonics adds its own complications. By Ed Sperling. #interconnects #semiconductor #advancedpackaging #photonics Intel Foundry Intel Corporation TSMC Samsung Semiconductor Letizia Giuliano Alphawave Semi Mick Posner Cadence Steven Tsai John Koeter Synopsys Inc Ramin Farjadrad Eliyan Corporation Michal Siwinski Arteris Todd Bermensolo Alphawave Semi ASE Global

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Visibl Semiconductors (YC W26) is building the first coordination layer for chip design. As chip teams scale, critical workstreams drift out of sync and issues surface late, driving costly delays ($XM+) and months of rework before tapeout. Visibl’s long-term vision is to build end-to-end AI systems that shrink chip design from years to weeks. The team is starting with coordination because that’s where design intent breaks first. Visibl was founded by Bryce Neil and Jordon Kashanchi, who have built production systems and custom AI chips at Microsoft, Intel Corporation, Arm, Deloitte OmniaAI, and SST. They started Visibl after repeatedly seeing coordination bottlenecks delay integration and tapeout. Seeing Visibl in action will change how your team approaches chip design. Book a demo at www.visiblsemi.com Congrats on the launch Bryce Neil and Jordon Kashanchi! https://lnkd.in/ghHgeqKZ

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WIRE-TO-WIRE: Stacking semiconductors in 3D requires tiny copper wires called TSVs (through silicon vias). But just how tiny can they get? Shuhang Lyu, Tiwei Wei, and Thomas Beechem are finding out: https://lnkd.in/gmNE3vtZ

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Cohu, Inc.'s Diamondx is an air-cooled universal semiconductor tester platform that can test the entire signal chain spanning power, RF, and MCU without spending unneeded platform overhead. Diamondx is one system for lab characterization & high-volume manufacturing, scaling from 5 to 40 slot systems that can test over 500 devices in parallel. To learn more, visit https://lnkd.in/dTuYQJn9

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Draper was named a member of the Intel Foundry Chiplet Alliance yesterday at the Intel Foundry Direct Connect event. The Chiplet Alliance will provide an assured and scalable path for customers looking to deploy designs that leverage interoperable and secure chiplet solutions for targeted applications and markets. “Revitalization of the U.S. microelectronics ecosystem is vital to our USMAG customer set. The Intel Foundry Chiplet Alliance provides a collaborative environment for trusted design services, IP development and advanced packaging solutions that meet our customers’ stringent national security requirements,” said Sarah Leeper, Vice President and General Manager, Electronic Systems at Draper. #DirectConnect #IntelFoundry

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