Join us for the Real Intent Workshop at DVCon U.S.. on the Expanding Role of Static Signoff in Functional Verification, with a special focus on glitch detection, connectivity, and security. (Thursday Feb 27th, Donner 11-12:30pm PST, DoubleTree Hotel San Jose)
Traditional simulation and formal verification methods rely heavily on boolean analysis, often leading to significant resource demands, slow analysis times, and capacity limitations. In contrast, static signoff employs abstract checking techniques, enabling early functional verification to overcome these limitations.
During the workshop, we will demonstrate how Real Intent's static signoff technology delivers effective, efficient, and accurate results for early RTL design and signoff.
-> Focus on Glitch Detection
We will showcase real-world examples of glitch-induced design failures identified by Real Intent's team, including:
- Glitches in asynchronous clock domain paths
- Glitches in reset paths
- Glitches in synchronous multi-cycle paths
- Glitches in power domain crossing paths and isolation signals
- Glitches at digital-to-analog interfaces
We will analyze each glitch type through detailed block diagrams, illustrating the identification, verification, and resolution processes.
-> SafeConnect for Advanced Connectivity Verification
- Conditional Connectivity Checking: Validating configurations like padmuxing.
- System and Configuration Registers: Validating connectivity and propagation of register values.
- Interrupt Verification: Ensuring critical one-to-one connectivity through specific sequential cells.
- Power Logic Connectivity: Validating correct power signal connections.
- Interconnect Reachability: Ensuring that signals can reach their intended destinations.
A standout feature of SafeConnect is its negative testing capability, enabling verification not only of correct connections but also ensuring that certain masters are not connected to specific slaves—a critical aspect often overlooked by other methods.
Sentry for Hardware Security Signoff
Spectre and Meltdown Mitigation: Sentry detects and addresses speculative execution vulnerabilities in x86, RISC-V, and ARM architectures, ensuring secure processor operation.
Hardware Roots of Trust: Validates critical security features, including:
Secure Boot: Ensures encrypted and authenticated assets remain protected.
Secure Enclave: Guarantees hardware isolation to protect sensitive data from unauthorized access and side-channel attacks.
Advanced Encryption Standards (AES) and Crypto Cores: Verifies AES-based cores for secure communications and data protection, ensuring that exposed signals do not compromise security.
Sentry redefines hardware security verification, making it an indispensable tool for RTL signoff. Integrating Sentry into your security workflow is key to ensuring robust, reliable design outcomes.
Meghana Desai Oren Katzir Will Philips Corey Fleischer Oren Dvir
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