QuickLogic Corporation

Trey Peterson, Applications Engineer at QuickLogic, will present: “Enabling Flexible Heterogeneous Integration with an eFPGA Chiplet on Intel® 18A.” He’ll discuss how eFPGA chiplets add post-silicon adaptability and help platforms evolve even at advanced nodes. 📍 Session E-202 🗓 Thursday, Feb. 19 | 3:00–4:20 PM #eFPGA #ChipletSummit #Intel18A #QuickLogic

Looking forward to Chiplet Summit in a few days. Meet us at the summit, and visit our Partner booths - QuickLogic and Sofics. And look for some exciting news coming during the show about breaking through the Chiplet Walls for adoption. #chipletsummit #sofics #quicklogic #AI #chiplets #UCIe #BoW #fpga #SOC #GPU #Memory

Heading to Chiplet Summit? QuickLogic will be there, exhibiting at Booth #416 and presenting on enabling heterogeneous integration using an eFPGA chiplet on Intel 18A. If you are exploring chiplets, flexible SoCs, or future-proof architectures, come talk with us. https://lnkd.in/gkAP4rBk #ChipletSummit #ASIC #SoCDesign #chiplets #eFPGA

Heading to Chiplet Summit? QuickLogic will be there, exhibiting at Booth #416 and presenting on enabling heterogeneous integration using an eFPGA chiplet on Intel 18A. If you are exploring chiplets, flexible SoCs, or future-proof architectures, come talk with us. https://lnkd.in/gkAP4rBk #ChipletSummit #ASIC #SoCDesign #chiplets #eFPGA

Chiplets Get Physical: The Days of Mix-and-Match Silicon Draw Nigh https://lnkd.in/eGkTWzGt Cadence is pushing chiplet technology forward with its Physical AI Chiplet Platform and ecosystem to help bridge today’s multi-die designs toward an open, interoperable future of scalable, mix-and-match silicon systems.

As SoCs move toward heterogeneous architectures and chiplets, programmable logic is no longer just a prototyping tool—it’s becoming a design-time decision. In this blog, QuickLogic breaks down the practical differences between FPGAs and embedded FPGAs (eFPGAs) from an implementation perspective: When a standalone FPGA makes sense for iteration, standards evolution, and field updates - Why eFPGAs integrated into an ASIC/SoC can deliver lower latency, better power efficiency, and smaller footprint - How on-die reconfigurable logic enables post-silicon flexibility without the cost and risk of a full respin - Architectural and system-level considerations engineers should weigh early in the design cycle If you’re designing custom silicon and thinking about how to preserve flexibility without sacrificing PPA, this is a useful comparison. 👉 Read blog at: https://lnkd.in/gQZjDH99 #FPGA #eFPGA #SoCDesign #ASIC #ChipArchitecture #SemiconductorEngineering #QuickLogic

Congratulations to YorChip Inc and Sofics on the joint press release announcing their UCIe PHY development optimized for Physical AI across TSMC nodes. 

QuickLogic has received initial orders for its Strategic Radiation Hardened FPGA Dev Kit, featuring test chips built on GlobalFoundries’ 12 nm process and targeting defense and aerospace applications. Read PR at https://lnkd.in/ebCBwjkG #QuickLogic #RadiationHardened #FPGA #AerospaceAndDefense #GlobalFoudries #eFPGA

🚀 50% lower energy. First-pass silicon. No re-spin. That’s what Epson achieved by moving critical workloads from software into QuickLogic eFPGA Hard IP on TSMC e12n. ⚙️ Architectural Choices: Customer-specific eFPGA Hard IP generated for e12n Low-leakage process + clock gating + tuned routing Clean integration and first-pass silicon success 📉 Result: ✔️ 50% improvement in overall energy efficiency ✔️ Higher performance headroom ✔️ Lower risk, faster schedule 👉 Full story in the blog - https://lnkd.in/gMHd8Hfh #eFPGA #SoCDesign #LowPowerDesign #FirstPassSilicon #HardwareAcceleration #Epson #TSMC

PHYSICAL AI is the hottest trend right now and YorChip was ahead of the game in developing Chiplets solutions for this market. Watch our Video on our Solutions for delivering on the promise of PHYSICAL AI. #AI #LLM #PHYSICALAI #Chiplets #UCIe #SOC #Packaging #SOC #FPGA #microcontrollers https://lnkd.in/gphRN99b