Régis SANTONJA

Chandler, Arizona, United States
957 followers 500+ connections

Join to view profile

About

In the semiconductors industry since 1994 (digital and analog)

Mixed-signal IC…

Activity

Join now to see all activity

Experience & Education

  • NXP Semiconductors

View Régis’s full experience

See their title, tenure and more.

or

By clicking Continue to join or sign in, you agree to LinkedIn’s User Agreement, Privacy Policy, and Cookie Policy.

Publications

  • AnaVip : an UVM component to drive and monitor analog signals

    Cadence MS Summit (San Jose CA)

    Basically same paper as previous one presented in Munich. I was asked wether I could present this UVM-MS compoenent in San jose (CA) : the "best paper effect" :-)

    See publication

  • Freescale Tracks Thousands of Simulations Before Tapeout for Bug-Free Silicon

    Cadence

    Regis Santonja, Senior Mixed-Signal Verification Engineer, Freescale Semiconductor discusses the challenge of drastically reducing the size of an accelerometer without compromising performance in terms of current consumption and noise, as well as transitioning to a UVM mixed-signal environment to introduce randomization to system-level simulations. By using Cadence® Incisive® vManager™ Solution to run and analyze thousands of simulations before tapeout, his team discovered and fixed 150 bugs…

    Regis Santonja, Senior Mixed-Signal Verification Engineer, Freescale Semiconductor discusses the challenge of drastically reducing the size of an accelerometer without compromising performance in terms of current consumption and noise, as well as transitioning to a UVM mixed-signal environment to introduce randomization to system-level simulations. By using Cadence® Incisive® vManager™ Solution to run and analyze thousands of simulations before tapeout, his team discovered and fixed 150 bugs, resulting in bug-free final silicon!

    See publication

  • [Best Paper Award] AnaVip: a UVM component to drive and monitor analog signals

    Cadence Live Conference 2015 Munich

    The Universal Verification Methodology (UVM) is today's most advanced verification methodology of digital integrated circuits. When extended to Mixed-Signal it is usually known as UVM-MS. In this context, Cadence provides a set of UVM components such as the "dms_wire" for sine-waves, and the "dms_ramp" for piece-wise linear shaped signals. However, the corresponding verilog-AMS "gaskets" are pretty basic, especially on the monitoring side. For example, the dms_wire requires the verification…

    The Universal Verification Methodology (UVM) is today's most advanced verification methodology of digital integrated circuits. When extended to Mixed-Signal it is usually known as UVM-MS. In this context, Cadence provides a set of UVM components such as the "dms_wire" for sine-waves, and the "dms_ramp" for piece-wise linear shaped signals. However, the corresponding verilog-AMS "gaskets" are pretty basic, especially on the monitoring side. For example, the dms_wire requires the verification engineer to provide a period and a duration to sample the sine wave so that its parameters (frequency, bias and amplitude) can be extracted. As such the verification engineer needs to have a clear idea of the signals max frequency to respect Shannon's law. The higher the clock frequency, the higher the precision... and the longer the simulation time. The AnaVip that we developped at Freescale uses a different approach based on sampling the signal when it changes by more than a user-defined precision. By this means, the simulation is faster : the number of samples varies with the slope, the faster the slope, the more the samples and vice versa. Additionally, there is no need to know the signal's maximum frequency anymore. The AnaVip is much straight forward to setup than Cadence's components and much more flexible. AnaVip is also able to monitor piece-wise linear signals. Furthermore, depending on the user-specified precision, real analog signals, whatever their shape, can be linearized (split into a piece-wise linear signal). Each linear piece detected triggers the UVC monitor to generate the appropriate transaction back to its subscribers within the testbench. For example, a regulator's output overshoot or ripples can be captured into bursts of transactions, allowing a scoreboard to check this behavior against the regulator's specification.

    See publication

  • [Best Paper Award] UVM Ready: Transitioning Mixed-Signal Verification Environments to Universal Verification Methodology

    DVCon Europe 2014 "Best Paper Award"

    This paper describes the transitioning of a module-based mixed-signal verification environment to
    Universal Verification Methodology (UVM). The result is a top-level mixed-signal verification framework that supports constrained-random verification and is backwards compatible to legacy module-based test cases. Thanks to a proxy systemVerilog® interface, the same mixed-signal drivers can be shared among the UVM test cases and the traditional module-based stimulus. Instead of wiggling signals…

    This paper describes the transitioning of a module-based mixed-signal verification environment to
    Universal Verification Methodology (UVM). The result is a top-level mixed-signal verification framework that supports constrained-random verification and is backwards compatible to legacy module-based test cases. Thanks to a proxy systemVerilog® interface, the same mixed-signal drivers can be shared among the UVM test cases and the traditional module-based stimulus. Instead of wiggling signals, the UVM drivers use task calls to outsource bus driving to the already existing module-based drivers. This methodology not only allows the re-use of UVM block-level components at the top-level, but also the integration of the UVM register layer and all its built-in tests. Furthermore, the methodology uses verilog configurations to elect the desired abstraction level of the design under test (DUT). All information required to describe a test case (i.e., stimulus, design configuration and simulation options) is gathered in one single file, thereby significantly improving test development.

    Other authors
    See publication

  • Re-usable Continuous-time Analog SVA assertions

    Cadence Live EMEA 2013

    This paper shows how SystemVerilog Assertions (SVA) modules can be bound to analog IP blocks, shall they be at behavioral or transistor-level, enabling the assertions to become a true IP deliverable that can be reused at SoC level. It also highlights how DPIs can fix analog assertions specificities, such as getting rid of hierarchical paths, especially when probing currents. This paper also demonstrates how to flawlessly switch models between digital (wreal) and analog models without breaking…

    This paper shows how SystemVerilog Assertions (SVA) modules can be bound to analog IP blocks, shall they be at behavioral or transistor-level, enabling the assertions to become a true IP deliverable that can be reused at SoC level. It also highlights how DPIs can fix analog assertions specificities, such as getting rid of hierarchical paths, especially when probing currents. This paper also demonstrates how to flawlessly switch models between digital (wreal) and analog models without breaking the assertions. Finally, it demonstrates how one can generate an adaptive clock to continuously assert analog properties whose stability over time is critical, such as current or voltage references or supplies.

    See publication

  • Mixed Signal Verification Challenges

    Cadence Live

    The increasing complexity of today’s Mixed-Signal Integrated Circuits (IC) goes with
    increasing needs in IC verification to ensure the functionality, but also signal integrity
    and power consumption. This paper is going to present the challenges of mixed-signal
    verification in its two main phases: simulation setting and coverage analysis on the
    other hand. In the mean time, it will present how, at Freescale, we took up these
    challenges during the development of a real-case Sensor…

    The increasing complexity of today’s Mixed-Signal Integrated Circuits (IC) goes with
    increasing needs in IC verification to ensure the functionality, but also signal integrity
    and power consumption. This paper is going to present the challenges of mixed-signal
    verification in its two main phases: simulation setting and coverage analysis on the
    other hand. In the mean time, it will present how, at Freescale, we took up these
    challenges during the development of a real-case Sensor IC, using Cadence eManager
    together with Verilog-AMS, SystemVerilog, and “wreal-based” digital models of the
    analog environment.

    See publication

  • Verification Of 1 M+ Transistors Mixed Signal I

    Cadence Live

    As the complexity and modularity of modern mixed-signal Integrated Circuits (IC)
    increase, together with the costs of masks and wafers, one needs to find new ways to
    simulate the IC’s behavior, signal integrity and power consumption before tape-out.
    This paper will demonstrate how, at Freescale, we take up this challenge by presenting
    the real case verification of a family of power-management ICs containing up to 1 million
    transistors, and more, with a wide variety of circuit…

    As the complexity and modularity of modern mixed-signal Integrated Circuits (IC)
    increase, together with the costs of masks and wafers, one needs to find new ways to
    simulate the IC’s behavior, signal integrity and power consumption before tape-out.
    This paper will demonstrate how, at Freescale, we take up this challenge by presenting
    the real case verification of a family of power-management ICs containing up to 1 million
    transistors, and more, with a wide variety of circuit topologies (linear analog circuits,
    switched mode supplies and audio system, high precision data converters, etc…).
    Most of the aspects involved will be presented, beginning with testbench architecture,
    then to regression tests, up through database management, test coverage, signal integrity,
    power consumption, etc…
    Historically, our initial goal was limited to functional verification. This paper presents
    our mixed-level simulation approach, based on some real case examples.
    However, some IC respins were caused by signal integrity problems, accidental leakages,
    or over consumptions. Indeed, the static current consumption requirements are getting
    more and more challenging, and the risk of leakages are increasing with the use of several
    voltage supplies that can be switched on or off independently. This paper presents how
    we manage to correlate simulated current consumption at IC level with silicon measures,
    and how we track potential floating nodes.

    See publication

  • Multi Supply Digital Layout

    SAME conference 2001 (Sophia Antipolis)

    See publication

Projects

  • Accelerometer

    -

    The MMA8451Q is a smart low-power, three-axis capacitive micromachined accelerometer with 14 bits of resolution. This accelerometer is packed with embedded functions with flexible user-programmable options, configurable to two interrupt pins. Embedded interrupt functions allow for overall power savings relieving the host processor from continuously polling data. There is access to both low-pass filtered data as well as high-pass filtered data, which minimizes the data analysis required for jolt…

    The MMA8451Q is a smart low-power, three-axis capacitive micromachined accelerometer with 14 bits of resolution. This accelerometer is packed with embedded functions with flexible user-programmable options, configurable to two interrupt pins. Embedded interrupt functions allow for overall power savings relieving the host processor from continuously polling data. There is access to both low-pass filtered data as well as high-pass filtered data, which minimizes the data analysis required for jolt detection and faster transitions. The device can be configured to generate inertial wake-up interrupt signals from any combination of the configurable embedded functions allowing the MMA8451Q to monitor events and remain in a low-power mode during periods of inactivity.
    --------------------------------------------------------------------------------
    Features
    --------------------------------------------------------------------------------
    1.95 to 3.6-volt supply voltage
    1.6 to 3.6-volt interface voltage
    ±2g/±4g/±8g dynamically selectable full-scale
    Output data rates (ODR) from 1.56 Hz to 800 Hz
    99 μg/√Hz noise
    14-bit and 8-bit digital output
    I²C digital output interface (operates to 2.25 MHz with 4.7 kΩ pull-up)
    Two programmable interrupt pins for seven interrupt sources
    Three embedded channels of motion detection Freefall or motion detection: one channel
    Pulse detection: one channel
    Jolt detection: one channel

    Orientation (portrait/landscape) detection with programmable hysteresis
    Automatic ODR change for auto-wake and return to sleep
    32 sample FIFO
    High pass filter data available per sample and through the FIFO
    Self-test
    RoHS compliant
    Current consumption: 6 μA–165 μA
    This product is included in Freescale’s product longevity program, with assured supply for a minimum of 10 years after launch

    Other creators
    • jean-claude mboli
    See project

  • Power Management and Audio Circuit

    -

    The MC13783 is a highly integrated power management, audio and user interface component dedicated to handset and portable applications covering GSM, GPRS, EDGE and UMTS standards. This device implements high-performance audio functions suited to high-end applications, such as smartphones and UMTS handsets.

    --------------------------------------------------------------------------------
    Features
    --------------------------------------------------------------------------------
    …

    The MC13783 is a highly integrated power management, audio and user interface component dedicated to handset and portable applications covering GSM, GPRS, EDGE and UMTS standards. This device implements high-performance audio functions suited to high-end applications, such as smartphones and UMTS handsets.

    --------------------------------------------------------------------------------
    Features
    --------------------------------------------------------------------------------
    Battery-charger interface for wall charging and Universal Serial Bus (USB) charging
    10-bit ADC for battery monitoring and other readout functions
    Buck switchers for direct supply of the processor cores
    Boost switcher for backlight and USB On-The-Go (OGT) supply
    Regulators with internal and external pass devices
    Transmit amplifiers for two handset microphones and a headset microphone
    Receive amplifiers for earpiece, loudspeaker, headset and line out
    13-bit voice codec with dual ADC channel and both narrow and wideband sampling
    13-bit stereo recording from analog input source such as FM radio
    16-bit stereo digital to analog converter (DAC) supporting multiple sample rates
    Dual synchronous serial interface (SSI) audio bus with network mode for connection to multiple devices
    Power control logic with processor interface and event detection
    Real-time clock (RTC) and crystal oscillator circuitry
    Dual serial peripheral interface (SPI) control bus with arbitration mechanism
    Multiple backlight drivers and LED control, including funlight support
    USB/RS-232 transceiver with USB carkit support
    Touch-screen interface
    247 BGA 0.5 mm pitch (10 mm x 10 mm) to optimize the size of the system
    Compatibility with CEA-936-A carkit regulation
    Integrated funlights and audio modulation features
    Capability to support two processor applications with dual SPI
    This product is included in Freescale’s product longevity program, with assured supply for a minimum of 10 years after launch

    Other creators
    See project

Languages

  • English

    Full professional proficiency

  • Spanish

    Limited working proficiency

Recommendations received

3 people have recommended Régis

Join now to view

More activity by Régis

View Régis’ full profile

  • See who you know in common
  • Get introduced
  • Contact Régis directly
Join to view full profile

Other similar profiles

Explore more posts

Explore top content on LinkedIn

Find curated posts and insights for relevant topics all in one place.

View top content

Add new skills with these courses

See all courses