Table of Contents

Introduction

The Xilinx® HDMI PHY Controller LogiCORE IP core is designed for enabling plug-and-play connectivity with Xilinx® HDMI™ 2.1 technology MAC transmit or receive subsystems. The interface between the video MAC and PHY layers are standardized to enable ease of use in accessing shared transceiver resources. The AXI4-Lite interface is provided to enable dynamic accesses of transceiver controls/status.

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Figure 1: Video IP layer

Driver Overview

The PHY is intended to simplify the use of serial transceivers and adds domain-specific configurability. The HDMI PHY Controller IP/Driver is not intended to be used as a stand alone IP and must be used with Xilinx Video MACs such as the HDMI 2.1 Transmitter/Receiver Subsystems and DisplayPort TX/RX Subsystems. The core enables simpler connectivity between MAC layers for TX and RX paths.

As such PHY Linux Driver is implemented within the kernel PHY framework and is tightly coupled with HDMI 2.1 Rx/Tx Linux drivers. This driver also hosts the common video files shared between the 3 Xilinx connectivity drivers (HDMI PHY, HDMI 2.1 Rx and HDMI 2.1 Tx) and exports the relevant API’s for inter-driver communication. On kernel boot-up both HDMI 2.1 Rx & Tx drivers will request 4 PHY lanes each for Rx & Tx and will defer until PHY driver has been initialized.

IP/Driver Features

HW IP Configuration

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Kernel Configuration Options for Driver

CONFIG_PHY_XILINX_HDMIPHY should be enable enabled in the kernel configuration.

Device Tree Binding

The dts node should be defined with correct hardware configuration. How to define the node is documented in

• 2025.2: Documentation/devicetree/bindings/phy/xlnx,v-hmdi-phy1.yaml

• 2025.1: Documentation/devicetree/bindings/phy/xlnx,v-hmdi-phy1.yaml

• 2024.2: Documentation/devicetree/bindings/phy/xlnx,v-hmdi-phy1.yaml

• 2021.2: Documentation/devicetree/bindings/phy/xlnx,v-hmdi-phy1.yaml

• 2022.1: Documentation/devicetree/bindings/phy/xlnx,v-hmdi-phy1.yaml

Below is the example device tree node generated by SDT for VCK190/VEK280/VEK385 platforms

The following system-user.dtsi entries need to be appended for various platforms to support onboard redriver components, which cannot be generated by the SDT tool.

• Below is the system-user.dtsi file used for designs targeting the VCK190, VEK280, and VEK385 platforms. This reference assumes that both the Rx and Tx data paths are enabled in the design.

• Below is the system-user.dtsi file used for designs targeting the ZCU102, ZCU106 platforms. This reference assumes that both the Rx and Tx data paths are enabled in the design.

DEBUG Capability

HDMI 2.1 PHY Linux driver implements the capability to tap IP status at pre-defined points in the control flow. User can enable the debug taps by uncommenting the pre-processor directive (#define DEBUG) to monitor the progress within the driver. All debug prints are sent to serial console and can be viewed in kernel dmesg buffer.

How to capture register dump

Create a script on target and name it as dumpmem.sh. Paste below content in that script.

Now run below command to dump the registers of Vphy

Boards Supported

Driver has been tested on following boards

• zcu102 Rev 1.0

• VEK280 Rev B03

Change Log

• 2025.2

  • Summary:

    • phy: xilinx-xhdmiphy: Add support for DPLL/MMCM clock primitive selection

    • phy: xilinx-xhdmiphy: Fix failing lower resolution modes on Versal Gen2 devices

• 2025.1

  • Summary:

    • phy: xilinx-xhdmiphy: Fix uninitialized variable use warning

• 2024.2

  • Summary:

    • phy: xilinx-xhdmiphy: Add support for selection of PLL/MMCM clock primitive

    • phy: xilinx-xhdmiphy: Fix FRL mode issue with versal devices

    • phy: xilinx-xhdmiphy: Fix video/link ready signals not getting asserted

• 2024.1

  • Summary:

    • phy: xilinx-xhdmiphy: Fix GT pll-selection allowed range of values

    • phy: xilinx-xhdmiphy: Fix function return types

    • phy: xilinx-xhdmiphy: Disable dru_clk in error path

    • phy: xilinx-xhdmiphy: Add pll-selection allowed range of values for GTYP/GTYE5

    • phy: xilinx-xhdmiphy: Configure HDMIPHY in TMDS mode

    • phy: xilinx-xhdmiphy: Configure retimer at FRL training linerate

    • phy: xilinx-xhdmiphy: Select FRL clock source after configuring in HDMI 2.1 mode

    • phy: xilinx-xhdmiphy: Clear all the config flags after being served

    • phy: xilinx-xhdmiphy: Fix configuring retimer chip in HDMI 2.1 mode

    • phy: xilinx-xhdmiphy: Add support for FRL 6G 3-lane mode

• 2023.2

  • Summary:

    • phy: xilinx-xhdmiphy: Reset the GTPLL before FRL training

• 2023.1

  • Summary:

    • phy: xilinx-xhdmiphy: Support duplex mode for GTYE5 and GTYP

    • phy: xilinx-xhdmiphy: Disable all the interrupts irrespective of direction

    • phy: xilinx-xhdmiphy: Get resolutions < 1920x1080@60 working

    • phy: xilinx-xhdmiphy: Make the rxch4-sel GPIO as an optional property

    • phy: xilinx-xhdmiphy: Add support for HDMI 2.1 pass-through mode

• 2022.2

  • Summary:

    • phy: xilinx-xhdmiphy: Add support to GTYE5 and GTYP devices

• 2022.1

  • Summary:

    • phy: xilinx-xhdmiphy: Set connector linerate in HDMI-RX TMDS mode

    • phy: xilinx-xhdmiphy: Fix connector linerate setting in FRL mode

Related Links

• Xilinx HDMI 2.1 FMC Card Linux Driver

• Xilinx DRM KMS HDMI 2.1 TX Subsystem Driver

• Xilinx V4L2 HDMI 2.1 RX Subsystem Driver