phy: xilinx-xhdmiphy: Add support for selection of PLL/MMCM clock primitive

Cost optimized devices have limitation of MMCM availability. HDMIPHY IP is
enabled with an option to select PLL or MMCM primitive for such resource
constrained devices. Add support in the driver to use output clocks from
the primitive type that IP is configured with.

Signed-off-by: Rajesh Gugulothu <rajesh.gugulothu@amd.com>
Reviewed-by: Vishal Sagar <vishal.sagar@amd.com>
State: pending

Author: gugulot

drivers/phy/xilinx/xhdmiphy.c

@@ -642,6 +642,34 @@ static int xhdmiphy_parse_of(struct xhdmiphy_dev *priv)
 	}
 	xgtphycfg->tx_maxrate = val;
 
+	rc = of_property_read_u32(node, "xlnx,rx-clk-primitive", &val);
+	if (rc < 0) {
+		dev_err(priv->dev, "unable to parse %s property\n",
+			"xlnx,rx-clk-primitive. Make MMCM as default value");
+		val = XHDMIPHY_MMCM;
+	}
+
+	if (val != XHDMIPHY_MMCM && val != XHDMIPHY_PLL) {
+		dev_err(priv->dev, "dt xlnx,rx-clk-primitive %d is invalid\n",
+			val);
+		return -EINVAL;
+	}
+	xgtphycfg->rx_clk_primitive = val;
+
+	rc = of_property_read_u32(node, "xlnx,tx-clk-primitive", &val);
+	if (rc < 0) {
+		dev_err(priv->dev, "unable to parse %s property\n",
+			"xlnx,tx-clk-primitive. make MMCM as default value");
+		val = XHDMIPHY_MMCM;
+	}
+
+	if (val != XHDMIPHY_MMCM && val != XHDMIPHY_PLL) {
+		dev_err(priv->dev, "dt xlnx,tx-clk-primitive %d is invalid\n",
+			val);
+		return -EINVAL;
+	}
+	xgtphycfg->tx_clk_primitive = val;
+
 	rc = of_property_read_u32(node, "xlnx,use-gt-ch4-hdmi", &val);
 	if (rc < 0) {
 		dev_err(priv->dev, "unable to parse %s property\n",

drivers/phy/xilinx/xhdmiphy.h

@@ -669,6 +669,7 @@
 #define XHDMIPHY_MMCM4_DRP_FILTER_REG2		0x4f
 #define XHDMIPHY_MMCM4_PWR_REG			0x27
 #define XHDMIPHY_MMCM4_WRITE_VAL		0xffff
+#define XHDMIPHY_PLL_WRITE_VAL			0x4401
 
 /* registers and masks of mmcme5 DRP */
 #define XHDMIPHY_MMCM5_DRP_CLKFBOUT_1_REG	0x0c
@@ -847,6 +848,11 @@ enum prbs_pat {
 	XHDMIPHY_PRBSSEL_SQUARE_16UI = 0xA,	/* square wave with 16 UI */
 };
 
+enum clk_primitive {
+	XHDMIPHY_MMCM = 0,
+	XHDMIPHY_PLL = 1,
+};
+
 enum xhdmiphy_mode {
 	tmds_mode = 0,
 	frl_mode = 1,
@@ -1018,6 +1024,8 @@ struct xhdmiphy_conf {
 	u8 gt_as_tx_tmdsclk;	/* use 4th GT channel as tx TMDS clock */
 	u8 rx_maxrate;
 	u8 tx_maxrate;
+	u8 rx_clk_primitive;
+	u8 tx_clk_primitive;
 };
 
 struct xhdmiphy_dev {