HDMI 2.1 PHY / GT Controller standalone driver
This page gives an overview of the common bare-metal driver support for the HDMI 2.1 PHY and GT Controller standalone driver.
Introduction
The Xilinx® HDMI PHY/GT Controller LogiCORE IP core is designed to enable plug-and-play connectivity with the Xilinx HDMI 2.1 MAC transmitter or receiver subsystems. The interface between the video MAC and PHY layers is standardized to enable ease of use in accessing shared transceiver resources. The AXI4-Lite interface is provided to enable dynamic accesses of transceiver controls/status. The PHY is intended to simplify the use of serial transceivers and adds domain-specific configurability.
The HDMI PHY/GT Controller IP/Driver is not intended to be used as a standalone IP and must be used with Xilinx Video MACs such as the HDMI 2.1 Transmitter/Receiver Subsystems and DisplayPort TX/RX Subsystems. The core enables simpler connectivity between MAC layers for TX and RX paths.
Driver Sources
The source code for the driver is included with the Vitis Unified Software Platform installation and is also available in the Xilinx Github repository.
Driver name | Path in Vitis | Parth in Github |
|---|---|---|
v_hdmiphy1 | <Vitis Install Directory>/data/embedded/XilinxProcessorIPLib/drivers/v_hdmiphy1 | embeddedsw/XilinxProcessorIPLib/drivers/v_hdmiphy1 at master · Xilinx/embeddedsw |
Note: To view the sources for a particular release, use the rel-version tag in GitHub. For example, for the 2025.1 release, the proper version of the code is: embeddedsw/XilinxProcessorIPLib/drivers/v_hdmiphy1 at xlnx_rel_v2025.1 · Xilinx/embeddedsw
The driver source code is organized into different folders. The table below shows the v_hdmiphy1 driver source organization.
Directory | Description |
|---|---|
src | Driver source files, make and cmakelists file |
doc | Provides the API and data structure details |
data | Driver .tcl, .yaml and .mdd file |
Note: the AMD Xilinx embeddedsw build flow has been changed from the 2023.2 release to adapt to the new system device tree-based flow. For further information, refer to the wiki link Porting embeddedsw components to system device tree (SDT) based flow
The .yaml file (in the data folder) and CMakeLists.txt file (in the src folder) are needed for the System Device Tree based flow. The Driver .tcl and .mdd files are for the older build flow which will be deprecated in the future.
Driver implementation
For a full list of features supported by this IP, see HDMI PHY controller PG333, HDMI GT controller PG334
HDMI 2.1 PHY IP Features
Protocol-specific functions for HDMI
HDMI clock detector
Use of fourth GT channel as TX transition minimized differential signaling (TMDS) clock source
Non-integer data recovery unit (NI-DRU) support for lower line rates
Independent TX and RX path line rates (device-specific)
Single quad support
Phase-locked loop (PLL) switching support from software
Transmit and receiver user clocking
Full transceiver dynamic reconfiguration port (DRP) accesses and transceiver functions
Advanced clocking support
AXI4-Lite support for register accesses
HDMI 2.1 GT Controller IP Features
AXI4-Lite support for register accesses
Protocol Support for HDMI 1.4/2.0 and HDMI 2.1
Full transceiver dynamic reconfiguration port (DRP) accesses to MMCME5
Independent TX and RX path line rates
Single quad support
Protocol-specific functions for HDMI:
HDMI clock detector
Use of fourth GT channel as TX TMDS clock source
Non-integer data recovery unit (NI-DRU) support for lower line rates
Added support for New GT Wizard Subsystem Implementation
Known issues and limitations
None
Example applications
None
Links to examples
None
Example application usage
None
change log
2025.1
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