7,448 questions
2
votes
0
answers
56
views
Difference between db string and other data sizes in assembly for strings [duplicate]
Assume this code in x86_64 assembly:
section .data
msg db "Hello, world!"
section .text
global _start
_start:
;; system call 1 is sys_write
mov rax, 1
...
- 133
2
votes
0
answers
116
views
x86 long mode setup issue
I am currently trying to make the second stage of a bootloader in order to enable 64 bit long mode. I have written some x86 assembly for the NASM assembler to do so, but when I compiled and ran the ...
2
votes
1
answer
101
views
printf wont work when linking to ucrtbase.dll, but works when linked to msvcrt.dll (Windows, NASM)
I am struggling to get printf to work for me in NASM while linking to ucrt.dll, It works 0 problems when I link to msvcrt.dll for printf, but I am trying to practice with something a little newer.
I ...
Advice
0
votes
1
replies
88
views
Branch predictor training depends on call site? (Spectre experiment)
While analyzing the Spectre vulnerability, I ran into a question about how branch prediction training works.
My understanding is that the CPU accumulates prediction history for a specific conditional ...
6
votes
1
answer
155
views
What is the purpose of the k0, k1, ... k7 registers?
I am debugging a simple program that prints the string "Hello, world!" three times. In the information about the registers that the gdb program gives, with the command info register, appear ...
- 63
1
vote
0
answers
120
views
How to compare a register and the effective address of a variable in GAS with intel_syntax
I am following an assembly tutorial where they use NASM. They manage to compare a register to a variable's address with cmp rcx, digitSpace, but how can I do the same with GAS?
As you know this ...
- 123
2
votes
1
answer
236
views
Kernel panic during ROP chain: GDB stepping mismatch and unexpected register state
I am working on a Linux x64 kernel exploitation CTF challenge. I have constructed a ROP chain to execute commit_creds(prepare_kernel_cred(0)).
However, I am encountering a major inconsistency between ...
- 1,401
1
vote
0
answers
200
views
How can I bypass the ASLR c code that was compiled as 64-bit? (school assignment : “within 10 minutes.”)
How could I get past it if the code is compiled as 64-bit? There’s no need to obtain a root shell; it’s sufficient to just verify that the address was guessed correctly. In my assignment, to bypass ...
- 1
27
votes
2
answers
2k
views
Why does clang zero "eax" before calling a function with unspecified parameters, but gcc doesn't?
Consider this C (not C++!) code:
int g();
int f() {
return g();
}
Clang (with any optimization level above zero) compiles this to:
f:
xor eax, eax
jmp g@PLT
I am trying ...
- 11k
Advice
3
votes
5
replies
105
views
x86_64 AT&T style assembly manual
I'm looking for an assembly language manual for x86_64 architecture that uses the AT&T style. Is such manual available directly by AT&T? What I found was from [Oracle](https://docs.oracle.com/...
- 595
6
votes
1
answer
164
views
What is the performance effect (on x64) of __atomic_fetch_add that ignores its result?
My code is
...
fragment1 // compares several regions in D1$ to D1$/D3$
__atomic_fetch_add(&lock,-1,__ATOMIC_ACQ_REL); // stmt A
fragment2 // moves several regions from D1$/D3$ to D1$
...
- 101
Advice
0
votes
4
replies
237
views
Why does GCC transform a >= 4 into a > 3 at -O0? JG seems to be more complex than JGE
Title: Why does GCC transform a >= 4 into a > 3 at -O0? JG seems more complex than JGE
I'm analyzing a simple C code on godbolt and found GCC's code generation puzzling:
long a;
a = a >= 4;
...
- 27
Best practices
1
vote
2
replies
115
views
Loading a byte: Partial register stall for intel cpus (r8 vs r64)
My assembly program reads characters in a text file by loading them one by one in register 'al'. However I sometime need to use rax fully, and I think this causes a partial register stall. Now I think ...
- 41
3
votes
2
answers
141
views
How can I correctly load the kernel to its canonical high address space
I am working on a small os with a custom boot loader targeting BIOS. For this, I need to map the kernel to its canonical high address space (0xFFFFFFFF80000000) and jump to its entry point.
For this, ...
- 133
0
votes
0
answers
52
views
How to cross-compile a customized QGroundControl (Qt 6.8.3) for Jetson Nano (ARM64) from Ubuntu x86_64
I have been customizing QGroundControl and have successfully built it for my Ubuntu system (x86_64 architecture) using Qt 6.8.3. I utilized the provided shell scripts and Dockerfiles located in the ...
- 39