Nishant Kumar

AMD to make Malaysia global hub for advanced chip design and packaging : https://lnkd.in/eAZDFkCx Speaking at the launch of the Emera Caribbean Renewables Limited (ECRL) operations and maintenance training programme, Prime Minister Datuk Seri Anwar Ibrahim said AMD — the world’s largest semiconductor company — aims to move beyond traditional backend work. - Malaysia is rapidly emerging as a preferred destination for high-value investments. Anwar’s comments come amid a surge in global interest in Malaysia, with countries such as Japan, Bahrain, the United States, and China deepening ties in investment, technology, and energy cooperation. #semiconductor #manufacturing #technology #innovation #chips  #semiconductormanufacturing #advancedtechnology #engineering #lithography #nanometer #research #development #AI #EUV #DUV #mobileprocessors #semiconductorindustry #semiconductormarket

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Silicon Labs is extending our sub-GHz portfolio with the new FG23L SoC. This “Lite” variant is optimized for long-range, ultra-low-power IoT devices that need secure, cost-effective connectivity. Get the full details on FG23L here: https://lnkd.in/gMuHp6A4 

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Silicon Labs just announced the FG23L, the latest addition to our Series 2 portfolio. Dev kits are available now and full GA is set for September 30. FG23L brings long-range sub-GHz connectivity, ultra-low power, and built-in security at a fraction of the cost of comparable solutions. It’s designed for applications like industrial sensors, smart cities, and building automation where range, efficiency, and cost all matter.

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Micron Technology starts building new 3D NAND fab in Singapore – Fab 10B promises to more than double the company's local flash production capacity Micron this week announced that it had begun construction of a new advanced wafer fabrication facility in Singapore, which will take over 10 years to completely build and will cost about $24 billion. The new fab will produce #3DNAND #memory with initial wafer output sometimes in the second half of 2028. The new Fab 10B is being built at Micron's existing 3D NAND manufacturing campus in North Coast Wafer Fab Park in Singapore and is designed to deliver up to 700,000 square feet of cleanroom space once it's fully built out. To put the number into context, Micron's Fab 10A and Fab 10X have a cleanroom space of around 500,000 square feet, so the new Fab 10B will more than double Micron's 3D NAND capacity in Singapore. "This investment underscores Micron’s long-term commitment to Singapore as an important hub in our global manufacturing network, enhancing supply chain resiliency and fostering a vibrant ecosystem for innovation," said Manish Bhatia, executive vice president of global operations at Micron Technology. https://lnkd.in/ePwMM4sw Personal addition 🤓: Hey cool. This means in 10 years we may have overcome the allocation/shortage 🤣 I hope that even the ramp up quantities in 2028 will help. #embedded #embeddedsystems #storage #electronics #SSD #semiconductor #memory #NAND #DRAM #technology #IIOT #industry40 #automation #automotive

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Micron broke ground on a new $24B advanced wafer fab in Singapore, marking a planned investment to expand NAND flash capacity. The fab is expected to begin wafer output in the second half of 2028.

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Cutting ASIC verification time by 75% is no small feat, especially when dealing with the complexity of asynchronous clocks in chip design. Lisa from Northrop Grumman highlighted the challenges of clock analysis, emphasizing the importance of early issue detection in the design process. Partnering with Siemens EDA (Siemens Digital Industries Software), Northrop Grumman's microelectronics team leveraged #AI powered Clock Domain Crossing (CDC) analysis tools, part of the Questa One Smart Verification solution. This strategic collaboration resulted in a significant reduction in clock analysis time, from eight weeks down to just two weeks. ✨ 🔗 Northrop Grumman continues to push boundaries in aerospace and defense, showcasing how advancements in clocking technology are revolutionizing possibilities in these critical industries. To learn more about their transformative journey, visit the link below. https://lnkd.in/gm5pezKU Feel free to DM me, if you are working on advanced ASIC and FPGA designs for aerospace and defense applications and would like to leverage AI/ML to improve your team's productivity. #Security #Innovation #ASICdesign #Defense #AIML

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Samsung reportedly plans 50% HBM output surge through 2026 💡🤖 Samsung Electronics plans to boost its high-bandwidth #memory (#HBM) production capacity by approximately 50% through late 2026, according to South Korean media outlet ET News, as the company secures key technical milestones with major #AI customers. #Samsung aims to reach a monthly output of 250,000 #wafers by the end of 2026, an increase from current levels of roughly 170,000 wafers. The South Korean #technology giant finalized the #investment decision this month and intends to begin full-scale capital expenditures early next year. The project involves converting current production lines and adding new capacity at its #Pyeongtaek campus, specifically within the P4 fab. Equipment #manufacturers anticipate receiving tool orders as early as next month because qualification testing for essential manufacturing #hardware is nearing completion, according to people familiar with the matter. Thanks again to Sherri Wand , Jessica Tsai and DIGITIMES Asia for the full article with more background and insights via the link below 💡🙏👇 https://lnkd.in/d4-hUmji #semiconductorindustry #semiconductormanufacturing #technololgy #it #tech #chip #korea #dram #server #datacenter #geopolitics #computer

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Memory Shortage: DDR5 RAM Prices Increase Again, Leading to a Per-GB Price Hike. With DDR5 RAM prices rising again, we might soon quote memory like gold — Per-GB (PG) instead of per gram. In the digital age, data is wealth and memory is the vault. Soon, engineering will grow where memory is scarce — because every shortage fuels innovation, efficiency, and smarter design.

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Malaysia is on a mission to grow its semiconductor sector and it starts with talent. At Penang Chip Design Academy (PCDA), we're helping future engineers gain real-world skills in IC design through industry-backed training, tools, and mentorship. Learn more about Penang Chip Design Academy - https://lnkd.in/gk7P-jJw Penang Silicon Design @5km+ (PSD@5km+) initiative is a transformative collaboration between government, academia, and industry, spearheaded by InvestPenang. It aims to drive innovation, accelerate the AI revolution, and position Malaysia as a leading global force to provide a complete end-to-end solution for the silicon industry. #PSDC #PCDA #PSD5KM #PenangSiliconDesign #InvestPenang Citation: 【¹】Source: Malaysia Semiconductor Industry Association (MSIA), MITI — National Investment Aspirations & NIMP 2030 targets.

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PCI Express Loopback: A Simple Concept with Powerful Verification Value In high-speed interconnect validation, PCI Express (PCIe) loopback is one of the most practical mechanisms for early bring-up, debug, and compliance verification. While often mentioned briefly, its real value becomes clear when viewed from a verification and system debug perspective. What Is PCIe Loopback? At a high level, PCIe loopback is a mode where transmitted data is routed back to the receiver. This allows validation of data paths without requiring a full external link partner and enables focused testing of specific blocks. Common PCIe Loopback Types • PHY Loopback Data is looped back at the physical layer. This is widely used for signal integrity validation, early PHY bring-up, and stress testing at high data rates. • MAC or Controller Loopback Loopback occurs at the protocol or controller level and helps validate packet formation, ordering rules, CRC handling, and LTSSM behavior. • External Loopback Signals are looped using cables, connectors, or test fixtures and are commonly used during board-level and system validation. Equalization Using Loopback One of the most important uses of PHY loopback is equalization tuning and validation. Loopback allows transmit and receive equalization settings to be exercised in a controlled environment without variability from another device. Using loopback, engineers can: • Tune TX de-emphasis or preset values • Validate RX CTLE and DFE behavior • Measure eye quality and BER trends across settings • Debug equalization convergence issues early This is especially critical for higher PCIe generations where PAM4 signaling, FEC, and tighter margins make equalization stability a first-order concern. Why Loopback Matters in Verification Loopback enables: • Early validation without a second device • Isolation of transmit versus receive issues • Faster LTSSM bring-up and debug • Controlled testing of error handling and recovery • Efficient compliance and regression testing Pre-Silicon and Post-Silicon Value • Pre-Silicon Used in simulation and verification IP environments to validate RTL logic, protocol sequencing, equalization flows, and corner cases. • Post-Silicon Helps isolate PHY, board, or system issues during lab bring-up, margining, and compliance testing. Key Takeaway PCIe loopback is not just a debug convenience. It is a foundational verification strategy that improves bring-up efficiency, reduces risk, and increases confidence across the entire development lifecycle. As PCIe continues to scale in speed and complexity under standards driven by PCI-SIG, effective use of loopback and equalization techniques becomes increasingly important for first-pass silicon success. #PCIe #PCIExpress #VIP #VerificationIP #Synopsys

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