Boddu Tejaswi

HW Bytes Post #6: BIRA & BISR in DFT - Memory Repair Essentials I was chatting with Copilot to refresh my memory on BIRA and BISR in DFT this week, and here are some basics I put together along the way:  #DesignForTestability #VLSI #SemiconductorTesting #ChipDesign #ASIC #SoC #ScanChain #BIST #BoundaryScan #ATPG

164

🚀 𝐔𝐧𝐥𝐨𝐜𝐤𝐢𝐧𝐠 𝐭𝐡𝐞 𝐅𝐮𝐭𝐮𝐫𝐞 𝐰𝐢𝐭𝐡 𝐕𝐋𝐒𝐈 𝐒𝐞𝐦𝐢𝐜𝐨𝐧𝐝𝐮𝐜𝐭𝐨𝐫𝐬 𝐃𝐨𝐰𝐧𝐥𝐨𝐚𝐝 𝐏𝐃𝐅 𝐁𝐫𝐨𝐜𝐡𝐮𝐫𝐞:https://lnkd.in/gS4e6WWA The VLSI Semiconductor Market is on a strong growth trajectory, valued at USD 60.71 Bn in 2024 and projected to reach nearly USD 97.49 Bn by 2032 at a CAGR of 6.1%. Very-large-scale integration (VLSI) technology revolutionizes integrated circuits by fitting millions of MOS transistors onto a single chip, optimizing space, efficiency, and performance. With rising demand in consumer electronics, automotive, healthcare, and communication sectors, the market is fueled by smart device adoption, electric and hybrid vehicle growth, and the increasing need for advanced semiconductor manufacturing. As industries embrace cutting-edge innovation, VLSI continues to power the backbone of modern electronics. 𝐕𝐋𝐒𝐈 𝐒𝐞𝐦𝐢𝐜𝐨𝐧𝐝𝐮𝐜𝐭𝐨𝐫 𝐌𝐚𝐫𝐤𝐞𝐭 𝐊𝐞𝐲 𝐏𝐥𝐚𝐲𝐞𝐫𝐬 Applied Materials  NVIDIA  Intel Corporation  Texas Instruments  Micron Technology  Qualcomm  Broadcom Inc.  Advanced Micro Devices (AMD)  Marvell Technology  Synopsys Inc. #VLSI #Semiconductor #ICDesign #Microelectronics #TechInnovation #SmartDevices #AutomotiveElectronics #BoycottHDFCBank #MusicUrZone #Cardi #TamannaahBhatia #ConsumerElectronics #HealthcareTech #CommunicationTechnology #HybridVehicles #ElectricVehicles #MEMS #ChipDesign #NextGenTechnology #ElectronicsIndustry #DigitalTransformation #SemiconductorMarket #AdvancedTechnology #FutureOfTech

266

Floorplanning Steps in Physical Design (VLSI) 👇 🧩 1. Define Die Size and Core Area Determine chip size based on utilization, aspect ratio, and target density. Allocate margins for IO pads, power rings, and routing. 🧱 2. Macro Placement Place large blocks (SRAMs, PLLs, analog macros, etc.). Ensure proper spacing for routing channels and power straps. Follow orientation and blockage rules. ⚡ 3. Power Planning Create power rings around core and macros. Add power stripes (VDD/VSS) across the core. Check IR drop and electromigration early. 📍 4. IO Placement Arrange input/output pads along the periphery. Follow package and ESD requirements. 🧮 5. Pin Placement Assign internal pins for macros and standard cells. Optimize for signal flow and timing. 🔒 6. Placement Blockages and Keepout Zones Define blockages near macros and edges to prevent cell overlap. Reserve routing and buffer insertion space. 🧠 7. Floorplan Validation Check aspect ratio, congestion, and connectivity. Verify DRC, power distribution, and routing feasibility. ✅ 8. Save and Export Floorplan Once optimized, save DEF or floorplan database for placement stage. Check our Premium VLSI Courses : https://lnkd.in/g5kVruWq Best VLSI COURSE : https://lnkd.in/gqXWwB2f Join VLSI Jobs : Whatsapp Channel : https://lnkd.in/dHsz2TZh Download VLSI FOR ALL Community App : https://lnkd.in/dB_QDcHT FREE Mentorship : https://wa.me/918218599381 Call us on (+91)-9643070368 Apple Users App Link : https://lnkd.in/dA_7YmYJ Write us on info@vlsiforall.com #vlsiforall #vlsijobs #freshers #internship #vlsitraining #Semiconductor #Innovation #Technology #Beginners #Electronics #Engineering #VLSI #EmbeddedSystems #HardwareDesign #InternshipOpportunity #success #stories #testimonials #SOC #SystemOnChip #VLSI #SemiconductorIndustry #Innovation

216

3 Comments

🚀 𝐕𝐋𝐒𝐈 𝐒𝐞𝐦𝐢𝐜𝐨𝐧𝐝𝐮𝐜𝐭𝐨𝐫 𝐌𝐚𝐫𝐤𝐞𝐭: 𝐏𝐨𝐰𝐞𝐫𝐢𝐧𝐠 𝐭𝐡𝐞 𝐅𝐮𝐭𝐮𝐫𝐞 𝐨𝐟 𝐒𝐦𝐚𝐫𝐭 𝐓𝐞𝐜𝐡𝐧𝐨𝐥𝐨𝐠𝐢𝐞𝐬 🌐 𝐃𝐨𝐰𝐧𝐥𝐨𝐚𝐝 𝐏𝐃𝐅 𝐁𝐫𝐨𝐜𝐡𝐮𝐫𝐞:https://lnkd.in/gS4e6WWA The VLSI Semiconductor Market, valued at USD 60.71 Bn in 2024, is projected to reach nearly USD 97.49 Bn by 2032 at a CAGR of 6.1%. Driven by demand for consumer electronics, EVs, healthcare innovations, and 5G connectivity, VLSI technology is shaping the next era of computing. With advancements like EUV lithography, AI-driven applications, and rising investments in Asia-Pacific and North America, this market is set to revolutionize industries across the globe. 🌍 Asia-Pacific dominates the market with key players like TSMC, Samsung, Intel, NVIDIA, and Applied Materials driving innovation. Challenges include high production costs, complex design, and cyclical demand, but opportunities lie in advanced nodes (<7nm), chiplet architecture, and energy-efficient designs. 𝐕𝐋𝐒𝐈 𝐒𝐞𝐦𝐢𝐜𝐨𝐧𝐝𝐮𝐜𝐭𝐨𝐫 𝐌𝐚𝐫𝐤𝐞𝐭 𝐊𝐞𝐲 𝐏𝐥𝐚𝐲𝐞𝐫𝐬 Samsung Electronics Taiwan Semiconductor Manufacturing Co. SK Hynix Inc. MediaTek KIOXIA Holdings Corp. Semiconductor Manufacturing International Corp. ROHM Co., Ltd. DISCO Corporation ASE Technology Holding Co. ASM Pacific Technology Vanguard International Semiconductor Corp. Renesas Electronics Corporation #VLSISemiconductor #SemiconductorIndustry #ChipDesign #AI #5G #IoT #TeachersDay #PunjabFloods #Cowboys #Messi #Eagles #BiharBandh #EdgeComputing #AutomotiveElectronics #SmartTechnology #AsiaPacificGrowth #TSMC #Intel #NVIDIA #Samsung #AppliedMaterials

11

🌟 Greetings Connections! Day 23 – Signal Integrity Signoff 🚀 Today’s topic is all about ensuring clean and reliable signals before a chip goes for tapeout. Signal Integrity (SI) signoff focuses on verifying that noise, glitches, crosstalk, and waveform distortions do not affect the logic behavior of the design. 🔍 What is Signal Integrity Signoff? Signal Integrity Signoff is the final stage where we check how signals behave on real wires under real conditions. Because as technology scales, wires become thinner and more sensitive — making unwanted effects like crosstalk, overshoot, undershoot, delay variations, and coupling noise more common. ⚡ Key Checks Performed: Crosstalk Noise Analysis: Ensures aggressor nets don’t inject unwanted glitches on victim nets. Glitch Verification: Confirms no small pulses trigger false logic switching. Crosstalk Delay Impact: Checks if coupling slows down or speeds up critical paths. Waveform Integrity: Ensures signal levels remain within safe thresholds. Dynamic Noise Checks: Ensures power noise or switching activity doesn't corrupt data. 🎯 Why This Matters? Even a tiny glitch can flip a bit or cause a functional failure in silicon. SI signoff ensures: ✔ Reliable timing ✔ Stable signal behavior ✔ Zero functional surprises in silicon ✔ A robust, tapeout-ready design ✨ Proper SI signoff = Peace of mind before tapeout! 🙏 Thank you for reading! Stay tuned for more learning updates in this RTL-to-GDSII journey. 🔖 #Day23 #SignalIntegrity #ChipDesign #VLSI #PhysicalDesign #Semiconductors #TapeoutReady #Crosstalk #GlitchAnalysis #ASICDesign #LearningJourney #EngineeringCommunity #AdvanceVLSI #LinkedInPost

21

Silicon Labs is extending our sub-GHz portfolio with the new FG23L SoC. This “Lite” variant is optimized for long-range, ultra-low-power IoT devices that need secure, cost-effective connectivity. Get the full details on FG23L here: https://lnkd.in/gMuHp6A4 

11

Namaskaram VLSI Folks 🙏 ✦✦✦✦✦ Factors That Affect Congestion in the CTS Stage ✦✦✦✦✦ Clock Tree Synthesis (CTS) is one of the most critical and sensitive stages in the Physical Design flow — and if not managed carefully, it can be a major source of routing congestion. Here are the key factors that directly impact congestion during CTS: 📍 1. Clock Network Complexity 🔹 Large fanout clocks 🔹 Multiple clock domains 🔹 Clock gating logic 🔹 Deep buffer tree structures 🔹 Mesh/hierarchical clock styles 📌 Impact: More buffers and wider routes increase metal usage and congestion. 📍 2. Tight Timing Constraints 🔹 Very low skew targets 🔹 Slew and jitter control 🔹 Setup/hold balancing across corners 🔹 Insertion delay matching 📌 Impact: Routing becomes timing-driven, restricting flexibility → higher congestion. 📍 3. Floorplan Challenges 🔹 High cell density regions 🔹 Poor macro spacing 🔹 Lack of routing corridors 🔹 Blockages near clock sink clusters 📌 Impact: Clock buffers get squeezed into tight zones, causing detours. 📍 4. Design Rule & Routing Restrictions 🔹 Spacing rules and via limits 🔹 Preferred layer usage (e.g., clocks restricted to M6–M9) 🔹 EM, antenna rule compliance 📌 Impact: Forces the router to use limited paths, increasing congestion pressure. 📍 5. Tool & Flow Behavior 🔹 Buffer clustering by non-congestion-aware CTS 🔹 Poor skew balancing algorithms 🔹 Lack of metal layer planning 📌 Impact: Clock nets crowd around critical sinks, worsening congestion post-CTS. ✦✦✦Tips to Reduce CTS Congestion✦✦✦ ✅ Use congestion-aware CTS modes ✅ Reserve top metal layers for clock nets ✅ Spread sinks and reduce clustering ✅ Floorplan with clock planning in mind ✅ Check congestion after placement — not just after CTS 📚 Clock trees don’t just deliver timing — they can make or break routing. Let’s build them smart, not just fast. Thanks for reading! 😊 #VLSI #CTS #ClockTreeSynthesis #RoutingCongestion #PhysicalDesign

111

🚀 From Design to Reality: How Your Chip Comes to Life! 🔧💡 After completing Physical Design flow — 📐 Floorplanning 📍 Placement ⏱️ CTS 🔌 Routing ✅ Signoff — we generate the GDSII/OASIS file: the exact blueprint for manufacturing. But what happens next? Fabrication — the exciting phase where design becomes reality! ✨ 🔑 Key Inputs to Fabrication: 🗂️ GDSII/OASIS layout masks 🛠️ Foundry’s Process Design Kit (PDK) 📋 Tapeout signoff reports 🔒 Licensed IP blocks ⚙️ Fabrication Steps: 1️⃣ Ultra-pure silicon wafer prep 🧪 2️⃣ Photolithography: print mask layers with UV light 📸 3️⃣ Etching & material deposition 🔥🧱 4️⃣ Ion implantation (doping) ⚡ 5️⃣ Metallization for interconnects 🔗 6️⃣ Packaging & protection 📦 7️⃣ Rigorous testing: wafer & final chip 🧪✔️ ⚠️ Fabrication Challenges: 🔬 Atomic-scale precision at advanced nodes 🎭 Complex, costly multi-pattern masks 📏 Strict Design-for-Manufacturability (DFM) rules 🌡️ Process variations impacting yield 💸 High cost & time — errors cause delays 📉 Yield loss — some chips don’t pass quality 🌟 Why Fabrication Matters: Without fabrication, a perfect layout is just data. Fabrication turns months of design into a working silicon chip — the heart of every electronic device. ❤️💻 💡 For Physical Design Engineers: Understanding fabrication helps us build robust, manufacturable chips that meet performance, power, and yield goals. Let’s keep pushing the limits of silicon innovation! 🚀⚙️ #VLSI #PhysicalDesign #Fabrication #Tapeout #ChipDesign #Semiconductor #ASIC #DFM #Innovation #PDFlow

10

Day 3 : Memory & EDA Series SRAM vs ROM vs DRAM – Simple Comparison Each memory type has a specific purpose: 🔹 SRAM – Fast, volatile, used for cache 🔹 DRAM – High density, needs refresh, used as main memory 🔹 ROM – Non-volatile, fixed data, used for boot code Choosing the right memory depends on: ➡️ Speed requirement ➡️ Power budget ➡️ Area constraints ➡️ Data persistence A good SoC design is all about balanced memory selection. 💬 Which memory type do you work with most? #MemoryArchitecture #SRAM #ROM #DRAM #EDA #VLSI

14

🚀 Roadmap for VLSI Freshers in Today’s Market 🧠💡 The VLSI industry is evolving rapidly, and while current market conditions may seem tough, opportunities still exist for those who stay consistent, skilled, and visible. Here's a roadmap to help freshers navigate and thrive in the semiconductor landscape: 🔍 1. Build Strong Fundamentals Ø Master Digital Electronics, CMOS, and VLSI design basics Ø Focus on Verilog/SystemVerilog, RTL design, and HDL simulation 🛠️ 2. Learn Tools & Flows Ø Get hands-on with EDA tools like Cadence, Synopsys, or Mentor Ø Understand basic ASIC/FPGA flow: Synthesis, STA, DFT, Physical Design 📚 3. Work on Real Projects Ø Build personal projects on GitHub or complete open-source tapeouts Ø Contribute to RTL design or verification tasks in small projects 📈 4. Stay Updated & Network Ø Follow semiconductor trends: RISC-V, AI Chips, Advanced Nodes Ø Connect with professionals, join VLSI forums, attend webinars 📄 5. Resume & Profile Optimization Ø Tailor your resume for specific job roles (Front-end, Back-end, Verification) Ø Keep your LinkedIn profile updated and active 💼 6. Internships & Training Ø Apply for internships and consider certified VLSI training programs Ø Even short-term real-world experience adds immense value 💬 7. Be Consistent & Patient Ø Rejections are part of the journey — don’t give up Ø Reach out to hiring managers and recruiters with a personalized pitch 🌱 Your learning mindset and persistence will be your biggest assets. If you’re a fresher looking for guidance, mentorship, or just want to connect with industry professionals — feel free to comment or message. Let's grow together. 💪 #VLSI #SemiconductorJobs #Freshers #CareerRoadmap #ASIC #FPGA #RTLDesign #PhysicalDesign #Verification #JobSearch #VLSICareer #BalachowdaiahParise

12

Crack FSM Design Questions Like a Pro! Just dropped a fresh video explaining some of the most commonly asked Finite State Machine (FSM) interview questions that appear in VLSI and digital design interviews. If you’ve ever stumbled on sequence detectors or wondered when to use Mealy vs Moore — this one’s for you! 🎯 What’s Covered in the Video? FSM for detecting the sequence 1010 (Overlapping & Non-Overlapping cases) Output toggling logic during detection Mealy vs Moore FSM – key differences with examples FSM design to check divisibility by 5 Whether you're prepping for a job interview, placement, or just brushing up your FSM skills — this will boost your confidence! 📽️ Watch the full video here: https://lnkd.in/gDyiispZ Let’s simplify FSMs together. 💡 Feel free to share it with someone preparing for their VLSI interviews! #FSMDesign #VLSIInterview #DigitalDesign #Verilog #MealyFSM #MooreFSM #SequenceDetector #FiniteStateMachine #VLSICareer #FPGA #RTLDesign #VLSITraining #TechInterview #EngineeringPrep

12

Memory paging in OS: Memory paging is a memory management scheme that eliminates the need for contiguous allocation of physical memory, thereby making more efficient use of available memory and simplifying memory allocation. 👉 Basic Idea 1️⃣ Paging: Divides the virtual memory into fixed-size blocks called pages and the physical memory into blocks of the same size called frames. 2️⃣ Virtual Memory: An abstraction that provides each process with the illusion of a large, contiguous address space. 3️⃣ Physical Memory: The actual RAM available in the system. 👉Key Components 1️⃣ Pages: Fixed-size blocks of virtual memory. Common sizes are 4 KB, 2 MB, or 1 GB. 2️⃣ Frames: Fixed-size blocks of physical memory that correspond in size to pages. 3️⃣ Page Table: A data structure used by the operating system to keep track of the mapping between virtual pages and physical frames. 👉 How Paging Works 1️⃣ Address Translation: When a program accesses a memory address, the virtual address is translated into a physical address using the page table. The virtual address consists of: Page Number: Indexes into the page table. Offset: Specifies the exact location within the page. 2️⃣ Page Table Lookup: The page table entry (PTE) for the page number provides the frame number. The frame number is combined with the offset to produce the physical address. 3️⃣ Page Faults: A page fault occurs if the required page is not in physical memory (not mapped to any frame). The operating system must bring the page from disk (swap space) into a free frame in physical memory and update the page table. 💪 Benefits of Paging 1️⃣ Eliminates Contiguous Allocation Requirement: Physical memory can be used more efficiently since any free frame can be used for any page. 2️⃣ Isolation and Protection: Each process operates in its own virtual address space, preventing one process from accessing the memory of another process. 3️⃣ Simplifies Memory Management: The operating system can manage memory in fixed-size blocks, simplifying allocation and deallocation. ✅ Summary Memory paging is a powerful technique that provides the benefits of virtual memory without the drawbacks of contiguous physical memory allocation. It allows systems to efficiently manage memory, ensure process isolation, and simplify memory allocation and deallocation through the use of fixed-size pages and frames. #paging #os #kernel #linux #embedded #learning #systemdesign

269

4 Comments

🔍 How to Reduce Delay / Insertion Latency? Delay or insertion latency can be reduced by replacing normal buffers with clock buffers at appropriate places. 🔹 Clock Buffer: •Clock buffers have same rise time and fall time. •This results in: •Less delay •Better signal quality across the chip •Clock buffers help to: •Reduce skew •Strengthen the clock signal 🔹 Normal Buffer: •Normal buffers do not have balanced rise and fall times. •Because of this: •They introduce more delay •They are not ideal for clock paths. -------------------- TELUGU VERSION 👇 -------------------- 🔍 Delay / Insertion Latency ni Ela Reduce Cheyali? Delay leka insertion latency ni reduce cheyadaniki, normal buffers ni remove chesi clock buffers use cheyali. 🔹 Clock Buffer •Clock buffers ki same rise time & fall time untayi •Dini valla: •Delay thagguthundi •Clock signal quality improve avutundi •Clock buffers help chestayi: •Skew reduce cheyadaniki •Clock signal ni strong ga maintain cheyadaniki 🔹 Normal Buffer •Normal buffers ki rise time & fall time same ga undavu •Anduke: •Delay ekkuva avutundi •Clock path ki suitable kaadu -------------- ✅ Summary •To reduce delay or insertion latency: Replace normal buffers with clock buffers •Clock buffers: •Have equal rise and fall times •Reduce delay and skew Normal buffers: •Cause more delay •Are not suitable for clock paths -------------- ONE LINE INTERVIEW ANSWER 👇 •Delay or insertion latency ni reduce cheyadaniki, normal buffers badulu clock buffers use chestham, endukante clock buffers ki same rise and fall time untayi kabatti delay and skew thagguthayi. #HASHTAG #ClockBuffer #ClockLatency #InsertionDelay #CTS #ClockTreeSynthesis #TimingAnalysis #ClockSkew #STA #VLSI #PhysicalDesign #ASICDesign #ChipDesign #BackendDesign #PlaceAndRoute

66