Nithin Kumar

Brief outline of the role of ASIC Verification that needs to be understood by someone willing to enter into this domain in VLSI: ✓ To understand the Architecture Specification and its functionality, design document understanding, Feature extraction plan, I/O port list details. ✓ Prepare the Verification Plan which includes the details of UVC's to be coded, functional description of the components - Driver, Monitor, Scoreboard, etc. ✓ Prepare the feature extraction plan and note the different features that needs to be verified. ✓ Preparing the TestPlan, identify the Directed and Corner case scenario. The Plan can be subdivided into Functional Test Cases, Connectivity Checks, Data and Control Path Checks, Register Testing, Low power checks, Constrained random tests. ✓ Start Coding the UVC's and when a basic Testbench Infrastructure is ready, verify it with a sanity TestCase. ✓ Code the Virtual Sequencer and corresponding virtual sequencer if there are multiple Agent Interface interacting with the DUT. ✓ Code the Scoreboard and there are multiple ways to do it either with tlm analysis fifo, set of queues and arrays, imp macros, etc. Might need to design an inorder or out of order comparator and it will check the integrity of Testbench. ✓ Build the RAL Layer and verify the different attributes of the register like RO, RW, WO, Special Register, etc. ✓ Use the Configuration wisely and start with coding more Test Scenario extending from Base Test or a library of Sequences. ✓ Prepare a Bug Rate Chart and usually at the initial level Bugs can be caught with the Directed Testcase.But once the Bugs start dropping it's the time to introduce Corner Cases, Functional Coverage and Assertions. ✓ Start Prepare a Assertion plan and initiate Functional and Code Coverage. Code Coverage will let you know how much Code has been exercised and Functional Coverage will deal with the Functionality. ✓ Identify the coverage holes and write more Testcases to cover the loopholes. Implement Checkers which are inbuilt in Assertions and it will help more in Verification. ✓ Testcases like Directed, Random, Corner case, needs to be executed for the thoroughness of verification. ✓ Running Regression with multiple seeds to check the probability of error and make sure the bugs are rectified. ✓ If a Testcase is failing with specific seed number, once that is rectified make sure to rerun the same seed and along with that other Testcases to make sure everything is fine. *** Different categories of Testcases *** a. Functional b. Connectivity c. Register d. CPU based e. Low Power f. Integration type g. Latency based h. Command training I. Reset and Clock j. Initialization. ****** **** Important points ***** a. Maintain coding guidelines. b. Judicious use of Objection mechanism. c. Testbench optimization wherever applicable. d. Proper use of p_sequencer or m_sequencer. e. Stress tests. ****** #vlsi #asic #electricalengineering

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Important Topics in VHDL / Verilog needed for internship / Entry level Professionals in VLSI: ✓ Event Queue in Verilog and how different Event regions are scheduled. ✓ Inter / Intra statement delay in Verilog. Execution flow of both Intra and Inter assignment using blocking and Nonblocking statement. ✓ Difference between Blocking and Nonblocking statement and the execution flow of both. ✓ How to avoid Race condition in Verilog. Time zero Races? Different types of Races. ✓ Problems in Verilog Full Case and Parallel case and how to avoid them. ✓ Different Wait statement in VHDL. Difference between Inertial Delay and Transport Delay. ✓ Difference between net and reg. Difference between Task and Function. Can we call a function inside a Task and a Task inside a Function. ✓ Port connectivity in Verilog. Vector Slicing. Use of `timescale and why timeprecision is needed. $display, $monitor, $strobe and $write execution. ✓ Difference between Signal and Variable in VHDL. ✓ Different flow of modelling the Code in Verilog / VHDL like Dataflow, Behavioral and Structural. ✓ Execution flow of fork..join and how it is different from Sequential execution. Execution for fork..join any / fork..join none ✓ Synthesizable construct for both VHDL and Verilog. Difference between VHDL an Verilog? How to enable assertions in VHDL. ✓ Code for overlapping and non-overlapping sequence detector using Mealy / Moore. Code for asynchronous and Synchronous reset of D FF. Code for count the no. of 1's, swapping the contents of variables. Priority Encoder and Counters (up - down, mod 10). ✓ Frequency Divider Circuit. Different ways of generating the clock. Clocking and Reset basics. ✓ Difference between casex and casez, initial and always block, assign and deassign, force and release. ✓ Importance of switch modelling and different UDP primitives. ✓ Self checking Testbench in Verilog. How to take care of randomization and constraints while writing Testbench in Verilog. ✓ Difference between Static and Dynamic Testbenches and Disadvantage of using Verilog as a Testbench Language. ✓ Difference between local param and defparam statements. Why Parameters and Constants are needed. ✓ Coding Guidelines to Follow. Why blocking statement is used in combinational and Non blocking are used in Sequential Circuits. Can we mix both. ✓ Difference between #0 and ##0. What is the use of Inactive Region. What are specparam statements. ✓ Execution flow in Translate and Optimise stage of Logic Synthesis. What are flattening and Factoring. What are Technology Libraries. ✓ Use of Generate statements. Delta Delay in VHDL. ✓ Different types of race around condition. Hardware race and Simulation race, read / write race, etc. #semiconductorindustry #vlsi #electricalengineering

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UVM is one of the most preferred methodology for verifying designs in VLSI and below are some of the points through which it can be learnt from the scratch. [1] Download UVM 1.2 Accellera User guide and go through it thoroughly to understand the below concepts. a. TLM understanding, Port export connection, Producer and Consumer connection, blocking and non blocking interface, and difference b/w TLM1 and TLM2. b. Transaction class and how to model it. Understanding of respective UVC's like Driver, Monitor, Sequencer, Scoreboard, Agent, Sequencer Driver interaction. Verification environment understanding and related coding of UVC. c. Use of virtual sequencer, virtual sequences, its necessity and controllability of multiple Agents. Arbitration Algorithms, Interrupts handling. d. Configuration mechanism and it's requirement, Test writing. e. Objection mechanism in UVM. f. Register Access Layer and it's usefulness in accessing registers. g. UVM Testbench infrastructure understanding, communication b/w each component and object. UVM phasing mechanism, UVM domain, phase jumping. [2] Download the UVM cookbook from verification academy and also go through the related concepts like a. UVM TB development and run test mechanism. b. Objection control mechanism and analysis components. c. Sequencer and Sequences. d. Modelling style of UVC. e. Sequence writing. f. Different types of scoreboard implementation. g. RAL h. Coverage Closure. [3] The next step is to put all the learning into practice. Take any simple IP like a memory controller or a FIFO and try to build a Verification environment. You can use edaplayground to test the code and one can also take the help of opencores webpage for any other project. Additional Concepts which are part of SystemVerilog: UVM is a BCL of SV and if often considered as superset. Hence the concepts of SV are applicable in UVM as well. Some imp concepts: a. CRV - All types of constraints b. OOP c. Assertions d. Clocking blocks e. Coding guidelines and SV Event Queue (Most Important) *** How to code a verification env in UVM from scratch will be covered in a separate post **** [4] Once the basics and fundamentals are clear, the next step is to learn further. For that download "The UVM class reference manual" and can have a look at following topics: a. UVM barriers. b. UVM domain, phase jumping, run time phases, user defined phases. c. Classes related to synchronization, triggering, etc. d. UVM resource db. e. Other classes that can be used to build TB framework. f. UVM callbacks [5] As a next step to enhance the learning someone needs to go through research papers, papers published in conferences, discussing with colleagues and mentors, etc. [6] Now it's required to download the IEEE UVM 1800.2 - 2017 LRM and to go through it to understand the new concepts and revise the old concepts. #vlsi #asic #semiconductorindustry #electricalengineering

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For Freshers Preparing for VLSI Design Verification Interviews: Every year, we interact with trained freshers aspiring to begin their journey in VLSI. The difference between those who succeed and those who struggle often comes down to one thing: clarity in fundamentals. Here’s what matters most: Strong basics → Digital Electronics, Verilog, SystemVerilog & UVM. Protocol awareness → If you mention it on your resume, be ready to answer at least basic questions on it. Theoretical clarity → You may not remember everything, but show that you understand 6–7 out of 10 topics you’ve been trained on. Code analysis → When an interviewer shows a snippet, don’t panic. Even if you don’t know the exact output, try to explain the concept and purpose. Thinking out loud matters. Training projects → Most of you have done projects during training. Know the flow, be clear on your contribution, and explain confidently. What causes rejections? Mentioning a project or protocol but not knowing the flow. Forgetting key UVM concepts like OOPs, factory, configuration, component vs. object. Saying “I saw it in training but I don’t know now.” My advice: Be confident in what you know, honest about what you don’t, and never underestimate the power of basics. Recruiters and hiring managers don’t expect you to know everything. But we do expect clarity, effort, and curiosity. That’s what gets you through the door. #VLSI #Semiconductors #Verification #Freshers #CareerGrowth #TalentAcquisition

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Clearing any RF Designer Interview: 1. Technical Proficiency: Review RF Fundamentals: Refresh your knowledge of key concepts like frequency, wavelength, power, gain, loss, linearity, modulation, bandwidth, and noise. Understand RF Design Principles: Be familiar with RF circuits and antenna design, propagation, link budgets, modulation schemes, and interference mitigation. Hands-on Experience: Be prepared to discuss your experience with industry-standard RF design tools and software. Specific RF Concepts: Be ready to explain concepts like impedance matching, signal integrity, and transmission line theory. Real-World Applications: Be prepared to discuss how you've applied these concepts to solve practical problems in areas like mobile communications, radar systems, or satellite communications. Troubleshooting: Be ready to discuss how you've diagnosed and resolved issues like signal degradation, unwanted capacitance, or interference. Explain Complex Concepts Simply: Demonstrate your ability to explain technical details clearly and concisely to both technical and non-technical audiences. Stay Updated: Show that you're aware of the latest trends and technologies in the RF field. 2. Project Experience: Highlight Challenges: Be ready to discuss specific challenges you faced during design or testing projects, such as technical limitations, regulatory issues, or tight deadlines. Describe Solutions: Clearly explain the technical solutions you implemented to overcome these challenges, including circuit design, simulation, or testing methodologies. Quantify Results: Whenever possible, quantify the results of your work, such as performance improvements, cost savings, or efficiency gains. Collaboration: Highlight your experience working with teams and stakeholders. 3. Soft Skills: Communication: Be prepared to explain technical details clearly and concisely to both technical and non-technical audiences. Problem-Solving: Demonstrate your ability to identify problems, analyze their root causes, and implement effective solutions. Teamwork: Highlight your ability to collaborate effectively with others. Adaptability: Show that you can adapt to changing requirements and work effectively under pressure. Enthusiasm: Express your genuine interest in the company and the specific role. 4. Interview Preparation: Research the Company: Thoroughly investigate the company's products, services, and design philosophy. Review Common Questions: Familiarize yourself with common RF engineering interview questions. Practice Explaining Concepts: Practice explaining complex RF concepts in simple terms. Prepare Examples: Have specific examples ready to illustrate your skills and experience. Be Punctual and Professional: Arrive on time and present yourself professionally. By focusing on these areas, you can significantly increase your chances of success in an RF Design Engineer interview. ALL THE BEST! 🙏🙏🙏🙏🙏

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🔍 Why Is VLSI Recruitment So Challenging? 🤔 If you've ever tried hiring in the VLSI domain, you know it’s no walk in the park. From sourcing to onboarding, it’s a tough game—and here’s why: 💡 1. Niche Skill Set: VLSI isn't just another tech buzzword—it’s a highly specialized field requiring deep knowledge in areas like digital design, verification, physical design, and semiconductor fundamentals. Not every engineer can make the cut. 📉 2. Limited Talent Pool: The number of engineers trained in VLSI (especially hands-on experience) is much smaller compared to general software roles. Even fewer have experience with industry tools like Synopsys, Cadence, or Mentor. 🏫 3. Gap Between Academia & Industry: Universities often focus on theoretical aspects, while the industry demands practical expertise. This disconnect makes it harder for fresh grads to be job-ready, slowing down the hiring funnel. ⚙️ 4. Long Training Time: Even if you find good candidates, ramping them up takes months. Companies are cautious because hiring the wrong candidate in a chip design role is costly—literally. 📍 5. High Competition: Big players, startups, and fabs alike are all fishing from the same pond. Good candidates are often snapped up before you even get through the interview process. 🎯 What's the way forward? Partner closely with academic institutions for curriculum alignment Offer internships & co-op programs to create a future talent pipeline Invest in upskilling passionate engineers from adjacent domains Streamline and speed up your hiring process Let’s talk about how we can make VLSI hiring more sustainable and scalable. Are you facing the same challenges? Drop your thoughts below! 👇 #VLSI #Semiconductors #HiringChallenges #TalentAcquisition #ChipDesign #EDA #VLSIHiring #Recruitment

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Getting ready for your RTL Engineer interview? Here are some basic RTL interview questions that can help you brush up your fundamentals before the big day: 1. What is the difference between blocking and non-blocking assignments in Verilog? 2. Explain the concept of synthesis vs simulation. 3. What are setup and hold times? Why are they important? 4. How do you model a combinational and sequential logic block in Verilog? 5. What is the difference between posedge and negedge in a sensitivity list? 6. How do you write a testbench for a simple design? 7. What are finite state machines (FSMs)? Can you explain Mealy vs Moore? 8. How would you avoid latches in RTL design? 9. Explain the concept of metastability. How do you handle it? 10. What are the differences between Verilog and SystemVerilog? These questions may look simple, but your ability to explain them clearly reflects how well you understand the core of digital design. Tip: Focus on writing clean, synthesizable RTL, and always think in terms of hardware! If you're preparing for RTL or Design Verification roles, drop a “YES” in the comments — I’ll share more interview prep content soon! #RTL #VLSI #Verilog #ChipDesign #RTLInterview #DesignEngineer #Semiconductors #Freshers #InterviewPreparation

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Why You MUST Learn AXI, AHB & APB to Crack Semiconductor Roles! #VLSICareers #SemiconductorJobs #AMBAProtocols #AXI #AHB #APB #SemiDesign If you’re aiming for a job in VLSI or SoC design/verification, there’s no escape from AMBA protocols – especially AXI, AHB, and APB. But what are they really, and why are companies like Qualcomm, Synopsys, Intel, and AMD obsessed with them? Let’s simplify it for you: ⸻ 1. AXI (Advanced eXtensible Interface) • Used for: High-speed, high-performance data paths – like between CPU and memory or interconnects • Features: • Supports multiple outstanding transactions • Out-of-order completion • Separate read/write channels • Why Learn It? Every modern SoC uses AXI. Whether you’re writing UVM testbenches or working on interconnects, AXI is everywhere. ⸻ 2. AHB (Advanced High-performance Bus) • Used for: Moderate-performance devices like DMA, on-chip RAM, or simple bridges • Features: • Supports burst transfers • Single master at a time, no pipelining • Why Learn It? AHB is the backbone of many legacy and mid-tier systems. If you’re working in embedded or IoT designs, AHB is your best friend. ⸻ 3. APB (Advanced Peripheral Bus) • Used for: Low-speed peripherals like UART, SPI, Timers • Features: • Simple interface, no burst • Lower power and area • Why Learn It? APB is the default choice for peripheral register accesses. If you’re writing register models, drivers, or SVA – APB is essential. ⸻ Why Are These Protocols Important for Your Career? Because interfacing is everything in chip design. From RTL to Verification, from IP to SoC level – understanding AMBA protocols helps you: • Design better RTL modules • Write accurate UVM environments • Debug faster in simulations • Stand out in interviews with real project-based knowledge ⸻ At Semi Design, we don’t just teach protocols — We show you how to implement, verify, and debug them in real industry projects. Want to build protocol-level confidence and crack interviews at top VLSI companies? Comment “AMBA” or DM us — and we’ll guide you! #SoCDesign #AMBAProtocols #ChipDesign #RTLDesign #UVM #VerificationEngineer #VLSITraining #SemiDesign

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10 must-know CMOS fundamentals questions for VLSI freshers (Interview-ready) If preparing for VLSI roles (design/verification/STA/PD), mastering CMOS basics is a huge differentiator. Here are 10 high-impact, conceptual questions interviewers love to ask freshers—plus what they’re really testing. 1.     Explain how a CMOS inverter works. ·       What happens in different input regions (0, transition, VDD)? ·       Why is CMOS static power ideally near zero? ·       What sets the switching threshold? 2.    Draw and explain the DC transfer characteristics of a CMOS inverter. ·       Define VIH, VIL, VOH, VOL and noise margins. ·       Where is the region of highest gain and why? 3.     What are the main sources of power consumption in CMOS? ·       Dynamic (switching + short-circuit), static (leakage types). ·       How do frequency, capacitance, and VDD impact power? ·       Practical ways to reduce each component. 4.    What is logical effort? ·       How it helps size gates for speed. ·       Parasitic delay vs effort delay; path effort intuition. ·       When not to trust it blindly. 5.     Explain body effect and its impact on VTH. ·       Why source-to-body matters (especially in bulk). ·       How it affects speed, leakage, and corners. ·       Differences in bulk vs SOI/FinFET contexts. 6.    Setup and hold time: what, why, and how violations occur. ·       Metastability and permissible timing windows. ·       Typical fixes (add pipeline, skew, sizing, Vt swap). 7.     Short-channel effects: DIBL, velocity saturation, channel length modulation. ·       How scaling changes I-V behavior and VTH. ·       Impact on delay, noise margins, leakage. 8.    What is PVT variation? How do corners affect design? ·       Process (SS/TT/FF), voltage, temperature. ·       Why timing closure needs best/worst corners and derates. ·       On-chip variation basics. 9.    Design a 2-input CMOS NAND (or NOR): transistor sizing and reasoning. ·       Series vs parallel stacking impact on pull-up/pull-down strength. ·       Matching rise/fall delays and W/L ratios conceptually. 10.  Explain the trade-offs between low-Vt, standard-Vt, and high-Vt cells. ·       Speed vs leakage vs IR/EM vs variability. ·       Multi-Vt strategies in real chips (critical vs non-critical paths). How to use this: ·       Don’t just memorize definitions—tie each question to waveforms, curves, or simple sketches. ·       Practice explaining in 60–90 seconds with clarity and structure. ·       If possible, connect answers to a small project or lab (e.g., “I measured inverter VTC and extracted noise margins…”). Also happy to mock interview for VLSI freshers. #VLSI #CMOS #Semiconductors #Freshers #Design #ASIC #FPGA #STA #PhysicalDesign #FrontEnd #BackEnd #EDA #Interviews

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Do you know what is verification matrices? This is most asked interview questions in experienced level DV interviews. Verification Metrics aren’t just numbers—they’re insights. They guide decisions, improve quality, and reduce risk. Coverage Metrics: Code & Functional Coverage Code coverage shows exercised RTL paths. Functional coverage tracks scenario completeness. Together, they reveal verification depth. Assertion Metrics: Assertion Pass/Fail Rates Assertions validate design intent in real-time. Track failures to catch corner-case bugs. High pass rate = stable design behavior Bug Metrics: Bug Rate & Closure Trends Monitor open vs. closed bugs over time. Spike in bug rate? Revisit test strategy. Closure velocity reflects team efficiency. Test Metrics: Test Pass Ratio & Runtime Pass ratio shows test stability. Runtime helps identify performance bottlenecks. Optimize for faster regressions. Simulation Metrics: Simulation Time & Performance Long simulations slow down feedback loops. Track sim time per test and per module. Use profiling to improve throughput. Coverage Closure: Coverage Closure Progress Set realistic coverage goals early. Track daily/weekly progress to avoid crunch. Closure = confidence in tape-out readiness. Metrics Drive Decisions Don’t just collect—analyze and act. Metrics help prioritize, debug, and optimize. Smart metrics = smarter verification. Do let me know what do you think and have you heard about it? Comment down 👇🏻👇🏻 Like, comment and follow Jatin Koshiya to see more content like this. #verificationmatrix #designverification #dv #interviews #dvinterviews #vlsijobs #hiring #rtl #verification #mentor #jatinkoshiya

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Many ask me — “Why a DV role?” My answer is simple 👇 Because each RTL failure tells a story — of design intent, hidden corner cases, and unexpected behavior. Every debug session makes me a better engineer, a sharper thinker, and a more patient learner. 🏌️‍♂️💫 In Design Verification, we don’t just find bugs — we learn from the failures. 💡 That’s why I love being in DV — it’s not just testing; it’s continuous learning. 🚀 #RISCV #CPU #RISCVDV

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Why Functional Coverage is the Secret Sauce in Verification 🎯 100% testing ≠ 100% coverage. Here's why functional coverage is non-negotiable in VLSI verification 🚀. Imagine you're testing a house security system 🏠 Code Coverage = "Did we test every door and window?" Functional Coverage = "Did we test breaking in through the front door while the alarm is ON during a power outage?" See the difference? 💡 What is Functional Coverage? → User-defined metrics measuring design behavior, not just code execution → Validates that specification features were properly exercised → Answers: "Did we test the scenarios that matter in real-world use?" Real-World Examples: 🔹 Data Coverage: "Did we test all packet sizes?" (Small packets, medium packets, jumbo frames) 🔹 Control Coverage: "Did we test the request-acknowledge handshake during system reset?" 🔹 Cross Coverage: "Did we test high-priority packets when the buffer is nearly full?" Why Code Coverage Isn't Enough: ✅ Code Coverage: "We executed every line of the FSM" ❌ Missing: "But did we test state transitions under error conditions?" ✅ Code Coverage: "We tested the interrupt handler" ❌ Missing: "But did we test nested interrupts during memory access?" House Analogy Extended: 🏠 Code Coverage: Checked that every room has a door 🎯 Functional Coverage: Tested security during storms, power outages, and simultaneous break-in attempts from multiple entry points The Reality Check: ➡️ 70% of verification effort goes to corner cases ➡️ 100% code coverage can still miss 40% of real bugs ➡️ Functional coverage reduces post-silicon surprises by 60% ➡️ Most chip failures happen in untested combinations, not untested code Pro Tips for Effective Functional Coverage: ✅ Define coverage goals before writing tests ✅ Focus on corner cases and error scenarios ✅ Test critical feature interactions (cross coverage) ✅ Target 90-95% functional coverage (100% often impractical) ✅ Review uncovered scenarios - are they reachable in real silicon? The Bottom Line: Code coverage tells you what code ran Functional coverage tells you what behaviors were verified In chip design, behavior verification prevents expensive silicon respins! 💰 Your turn: What's the most surprising bug functional coverage caught in your projects? Share your verification war stories! 👇 #SystemVerilog #VLSI #FunctionalCoverage #Verification #RTLDesign #ChipDesign #DigitalDesign #CoverageDrivenVerification

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Understanding AON vs ONO in Power Gating Power management is a key pillar in modern SoC design — especially as we push for higher efficiency in battery-operated and high-performance chips. Two terms often encountered in low-power VLSI design are: 1. AON (Always-On) These are the logic blocks that must remain powered at all times, regardless of the chip’s power state. Typically powered by a dedicated VDD_AON supply Used for critical operations — reset logic, PMU, always-on level shifters 2. ONO (On in Normal Operation) — Power Gated These blocks are powered only during active states and are shut down in low-power modes. Saves leakage power Controlled via power switches May require retention cells if state needs to be preserved In essence: AON → Always powered | ONO → Power gated Understanding and optimizing AON vs ONO domains is critical for hitting your power budgets without compromising functionality. #VLSI #LowPowerDesign #SoC #Semiconductor #PowerGating #ChipDesign #EDA #ASIC #AlwaysOn #PowerManagement #PhysicalDesign #Semiconductors

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Exploring a career shift into VLSI? Here's a quick-start guide. VLSI is a core field that requires both strong fundamentals and smart preparation. But the biggest challenge? Knowing where (and how) to begin. This 6-slide carousel breaks it down: 🔍 What companies actually look for in freshers 🧭 How to choose between frontend vs backend roles 🛠️ Essential skills and tools to get started 🏢 Entry-level roles and companies hiring now 📄 Resume tips for better visibility in applicant tracking systems (ATS) 🎥 Also, check out this useful VLSI interview prep video: 👉 https://lnkd.in/gHNW8zrH For anyone transitioning from electronics or embedded systems, this post offers clarity and direction to confidently take the next step. — #vlsi #chipdesign #frontendvlsi #backendvlsi #verilog #systemverilog #fpga #rtl #timinganalysis #edatools #hardwaredesign #vlsijobs #careertransition #engineeringjobs #atsresume #interviewprep #digitaldesign #vlsistudent #learnvlsi #jobsearchtips #freshersupport

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