Chirag Jalan

Design Verification Interview Questions @ Top Silicon Giants If you're aiming for Design Verification roles at companies like Intel, Qualcomm, AMD – or other titans like Apple, Nvidia, Google, Amazon (Annapurna Labs), Meta (Reality Labs), and Microsoft (Silicon Team) – this post is for you. Across my learning journey and from insights shared by candidates, mentors & friends in the industry, here are common themes and topics that consistently pop up in interviews: 🟡 Core SystemVerilog Concepts • Interface, Modport, Virtual Interface • Static vs automatic, randomize(), constraints • Deep dive into classes, inheritance, factory pattern 🟢 Assertions (SVA) • Immediate vs Concurrent • Property/sequence constructs • Vacuous success, overlapping/non-overlapping implications 🔵 UVM (Universal Verification Methodology) • UVM Phases, TLM1 vs TLM2 • Scoreboard, monitor, agent – when & how to use • Factory override, configuration DB • Sequences, virtual sequences & objections 🟣 Digital Design Fundamentals • FSM design/debug • Timing: setup/hold, metastability, clock domain crossing • Priority vs parallel case statements • Pipelining, hazards, throughput 🔘 Protocol Awareness (based on target team) • AXI, AHB, PCIe, USB, I2C, Ethernet • Cache Coherency basics (for CPU-related roles) • Memory hierarchy, MMU, TLB (for performance teams) Bonus Rounds (asked at BigTechs often): • Debugging waveform or testbench live • Write a constrained-random test • Code review or pseudo code optimization • How would you architect a TB from scratch? My Tip: Don’t just memorize answers. Build intuition – know why something works, not just how. 🔁 Save this post & reshare with peers who are prepping. Let’s crack the top DV roles together 💥 If you'd like a deeper dive on any topic (say SVA, Constraints, or UVM sequences) – drop a comment or DM. I’ll keep sharing what I learn 💡 #VLSI #DesignVerification #SystemVerilog #UVM #InterviewPrep #RTL #ChipDesign #Semiconductor #LinkedInTechFam

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Chip Validation is Broken—And It's Costing the Industry Billions NVIDIA ($2T market cap), Intel ($150B+), AMD ($300B) — all pushing the limits of chip design. But nobody’s talking about the hidden bottleneck slowing their progress: Validation inefficiencies that delay launches and burn resources. These aren’t isolated issues. They’re systemic failures. Before a chip hits the market, it undergoes extensive testing to ensure it performs as expected under real-world conditions. This process—chip validation—is crucial for verifying functionality, performance, and reliability. But validation today is painfully slow. Engineers spend weeks scripting and running tests manually, dealing with fragmented tools, and sifting through scattered data to debug issues. The result? Delays, inefficiencies, and skyrocketing costs. The Broken Playbook -Weeks spent scripting tests instead of analyzing results -Scattered data across tools, slowing debugging cycles -Manual processes introducing errors and inefficiencies Behind the cutting-edge innovation lies a brutal truth: Validation is stuck in the past the last software that was built for validation released in 2001 (LabView). The Future of Validation: A new era is emerging: Automated, AI-driven validation workflows. And the results are game-changing: 20x faster test execution Fewer errors, more actionable insights Seamless collaboration across teams At Atoms, we’re not just talking about the future—we’re building it: One platform to automate and accelerate chip validation AI-assisted workflows to streamline debugging Real-time insights for faster decision-making Because while traditional validation burns months, the companies of the future are already moving at light speed. The old methods had their time. The age of AI-powered validation has begun. #Semiconductors #ChipValidation #FasterTimeToMarket #TestFlow

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I was asked a simple yet intriguing question last week during my 1-on-1 mentorship call: 𝗪𝗵𝘆 𝘀𝗵𝗼𝘂𝗹𝗱 𝗮 𝘃𝗲𝗿𝗶𝗳𝗶𝗰𝗮𝘁𝗶𝗼𝗻 𝗲𝗻𝗴𝗶𝗻𝗲𝗲𝗿 𝗹𝗲𝗮𝗿𝗻 𝗥𝗧𝗟 𝗗𝗲𝘀𝗶𝗴𝗻? 𝗪𝗵𝘆 𝗰𝗮𝗻’𝘁 𝘁𝗵𝗲𝘆 𝘀𝗶𝗺𝗽𝗹𝘆 𝗳𝗼𝗰𝘂𝘀 𝗼𝗻 𝗰𝗹𝗮𝘀𝘀-𝗯𝗮𝘀𝗲𝗱 𝘁𝗲𝘀𝘁𝗯𝗲𝗻𝗰𝗵 𝗱𝗲𝘀𝗶𝗴𝗻, 𝗨𝗩𝗠, 𝗮𝘀𝘀𝗲𝗿𝘁𝗶𝗼𝗻𝘀, 𝗮𝗻𝗱 𝗳𝗶𝗻𝗱𝗶𝗻𝗴 𝗯𝘂𝗴𝘀? 𝗪𝗵𝘆 𝗯𝗼𝘁𝗵𝗲𝗿 𝘄𝗶𝘁𝗵 𝗥𝗧𝗟 𝗗𝗲𝘀𝗶𝗴𝗻 𝗮𝘁 𝗮𝗹𝗹? Early in my career, I had a similar mindset—I believed RTL Design wasn’t my responsibility, so it was okay if I didn’t fully understand how it was implemented or how it worked. But the moment I started learning RTL Design- I realised how wrong I was. Understanding microarchitecture, RTL design, implementation trade-offs, and writing synthesizable RTL helped me in several ways: • 𝗜 𝗯𝗲𝗰𝗮𝗺𝗲 𝗳𝗮𝗿 𝗺𝗼𝗿𝗲 𝗰𝗼𝗻𝗳𝗶𝗱𝗲𝗻𝘁 𝗶𝗻 𝗺𝘆 𝗱𝗲𝗯𝘂𝗴 𝗮𝗻𝗮𝗹𝘆𝘀𝗶𝘀.  • 𝗜 𝗰𝗼𝘂𝗹𝗱 𝘁𝗵𝗶𝗻𝗸 𝗼𝗳 𝗰𝗼𝗿𝗻𝗲𝗿 𝗰𝗮𝘀𝗲𝘀 𝗮𝗻𝗱 𝗻𝗲𝘄 𝘄𝗮𝘆𝘀 𝘁𝗼 𝗯𝗿𝗲𝗮𝗸 𝘁𝗵𝗲 𝗱𝗲𝘀𝗶𝗴𝗻.  • 𝗜 𝘄𝗮𝘀 𝗮𝗯𝗹𝗲 𝘁𝗼 𝘀𝘂𝗴𝗴𝗲𝘀𝘁 𝗯𝘂𝗴 𝗳𝗶𝘅𝗲𝘀, 𝘄𝗵𝗶𝗰𝗵 𝗱𝗲𝗲𝗽𝗲𝗻𝗲𝗱 𝗺𝘆 𝘂𝗻𝗱𝗲𝗿𝘀𝘁𝗮𝗻𝗱𝗶𝗻𝗴 𝗼𝗳 𝘁𝗵𝗲 𝗱𝗲𝘀𝗶𝗴𝗻 𝗮𝗻𝗱 𝗺𝗶𝗰𝗿𝗼𝗮𝗿𝗰𝗵𝗶𝘁𝗲𝗰𝘁𝘂𝗿𝗲. All in all, this helped me become a better verification engineer. That’s why I always recommend that verification engineers learn the basics of RTL Design—it will help you write better checks, debug failures more effectively, and uncover hidden bugs in the design. 𝗪𝗵𝗮𝘁 𝗱𝗼 𝘆𝗼𝘂 𝘁𝗵𝗶𝗻𝗸? 𝗦𝗵𝗼𝘂𝗹𝗱 𝘃𝗲𝗿𝗶𝗳𝗶𝗰𝗮𝘁𝗶𝗼𝗻 𝗲𝗻𝗴𝗶𝗻𝗲𝗲𝗿𝘀 𝗹𝗲𝗮𝗿𝗻 𝗥𝗧𝗟 𝗗𝗲𝘀𝗶𝗴𝗻? PS: Please DM if you are interested to know about the personalised mentorship :)

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ASIC vs FPGA – A Friendly Conversation Rahul: Bro, I’m confused! Should I go for ASIC or FPGA for my next project? Amit: Haha! That’s the classic debate. What’s your priority? Performance & cost or flexibility & quick prototyping? Rahul: I need high performance and low power consumption. Amit: Then ASIC is the way! Once fabricated, it’s super optimized. But remember, development takes time and is costly. Rahul: Hmm… What about FPGA? Amit: FPGA is like LEGO! 🧱 You can reprogram it, perfect for prototyping and low-volume production. But it consumes more power and is not as fast as ASIC. Rahul: Got it! So ASIC for mass production and FPGA for flexibility & development. Amit: Exactly! Both have their place in chip design. It depends on what you need. System-on-Chip (SoC): The Brain Behind Modern Tech! 💡 In today's fast-paced digital world, System-on-Chip (SoC) is powering almost everything around us - from smartphones and AI devices to automotive systems and IoT gadgets. 🔹 What is SoC? It’s a single chip that integrates CPU, memory, GPU, AI accelerators, and other essential components, making devices more compact, power-efficient, and high-performing. 🔹 Where is SoC used? Smartphones 📱 AI & Machine Learning 🤖 Automotive Electronics 🚗 Smart Wearables ⌚ IoT & Edge Computing 🌎 With the rise of AI, 5G, and autonomous systems, SoCs are redefining the future of modern technology. 🌐 Visit: https://provlogic.com/ 👉 👉 For more information do follow ProV Logic or Prasanthi Chanda #mentor #guidance #training #workshop #vlsi #internships #design #verification #masters #interview #physicaldesign #vlsidesign #coaching #chip #manufacturing #digital #analog #semiconductor

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🚀 Boost Your Referral Requests! 🚀 I've referred several hundreds of people to Qualcomm, from entry-level to senior roles. Here are some tips to make your referral request stand out: 1. Be Clear: Clearly state your goals and what you're seeking. 2. Share Smartly: Avoid sharing random Google Drive links. People are cautious about phishing. Instead, attach your resume directly to the email. 3. Catchy Subject Line: Use a subject line that grabs attention. Mention your skill set in it. 4. Mention Job IDs: Specify the Job ID that suits you. 5.Personalize Messages: Avoid generic messages like "Hi" or "refer me." Add some context. Either over email or LinkedIn. 6. Quality Matters: If your resume is good and your ask is clear, I personally share it with the hiring manager. Let's make the referral process smoother and more effective for everyone! 🌟 #JobSearch #CareerTips #ReferralTips #LinkedInTips #JobHunt #CareerAdvice #Networking #india #hiring #referral #career #jobs #software #hardware #vlsi #embedded #socialmedia #helpinghand #help

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𝐈𝐧𝐝𝐢𝐚’𝐬 𝐒𝐞𝐦𝐢𝐜𝐨𝐧𝐝𝐮𝐜𝐭𝐨𝐫 𝐇𝐢𝐫𝐢𝐧𝐠 𝐒𝐮𝐫𝐠𝐞 𝐢𝐬 𝐑𝐞𝐝𝐞𝐟𝐢𝐧𝐢𝐧𝐠 𝐂𝐚𝐫𝐞𝐞𝐫𝐬! The semiconductor industry in India is experiencing an unprecedented hiring boom — gradually chipping away at IT placements and opening exciting opportunities for engineers across domains. 🔹 End-to-end hiring: RTL/SoC design, verification, embedded systems, manufacturing (process, packaging, yield). 🔹 Freshers’ salaries: ₹6–12 LPA (vs. ₹3–4 LPA in IT). 🔹 Aggressive campus recruitment from tier-2 & tier-3 colleges, not just IITs. 🔹 Internships: ₹40k–50k/month stipends to build hands-on chip design skills. 🔹 Hiring scale: ~12,000 freshers annually (up from 8,000 last year). 🔹 Career growth: Roles extend up to ₹20–120 LPA for architects & leaders. Fuelled by global supply chain shifts, EVs, telecom, defence, and government initiatives (DLI, PLI, ECMS), this hiring surge is reshaping student aspirations, especially in ECE and core engineering branches. With India projected to hit $103B semiconductor market by 2030, this is the right time for students and professionals to align their skills with VLSI, Embedded Systems, AI/ML hardware, and semiconductor manufacturing. The future is semiconductor — and India is powering ahead as a global hub! https://lnkd.in/gKtU5Gn2 #Semiconductor #VLSI #ChipDesign #EmbeddedSystems #Electronics #SoC #SemiconductorIndia #SemiconductorJobs #SemiconductorTalent #HiringTrends #Careers #ECE #Engineering #SemiconductorEcosystem #MakeInIndia #Innovation #ElectronicsManufacturing #FutureOfWork #AI #ML #Hardware #Manufacturing #IndiaSemiconductorMission

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IN-ORDER SCOREBOARD In-order scoreboard is used when scoreboard output is in same order as the driven stimulus. It is implemented using UVM TLM FIFOs. Let's learn: 1. What is in-order scoreboard? 2. How to implement in-order scoreboard 3. Diagrammatic representation of in-order scoreboard 4. In-order scoreboard code IN_ORDER SCOREBOARD DETAILED VIDEO - LINK IN COMMENT #rtldesign #rtl #digital #digitalelectronics #digitalelectronics #lectures #computerengineering #computerarchitecture #vlsidesign #vlsi #vlsitraining #vlsijobs #vlsiprojects #verification #verificationengineer #physicaldesign #pd #physicaldesignengineer #semiconductor #semiconductorindustry #tcl #scipting #puzzles #problemsolving #career #careerdevelopment #careerguidance #resume #resumebuilding #resumereview #mentor #mentorship #vlsihelpinghands #switispeaks #switipinjani #coding #codinglife #codingtutorial #codingtips #codingjourney #programming #programmer #education #computer #guidance #interview #selfimprovement #selfdevelopment #motivation #careerdevelopment #careers #learning #sv #uvm #systemverilog #soc #ip #asics #cpu #processor #hardwaredescriptionlanguage #cpu #gpu #graphics #supercomputer #tutorial #quiz

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TSMC Vs Intel: What is the difference in business model ——————- 1. TSMC – Pure-Play Foundry Model • What it means: TSMC manufactures chips for other companies but doesn’t design or sell chips under its own brand. • How it works: Companies like Apple, Nvidia, AMD, and Qualcomm design chips → they send designs to TSMC → TSMC fabricates them in its fabs → ships them back. • Revenue source: Fabrication fees from multiple customers. • Risk profile: Design risks are borne by the customers; TSMC focuses on process technology and manufacturing efficiency. Example: Apple designs the A17 Pro chip for the iPhone. Apple gives the chip design files to TSMC → TSMC manufactures the chip using its 3nm process → Apple puts it in iPhones. If the A17 fails in the market, Apple suffers, but TSMC still gets paid for manufacturing. ⸻ 2. Intel – Integrated Device Manufacturer (IDM) Model • What it means: Intel both designs and manufactures its chips, selling them under its own brand. Recently, it is also trying to act as a foundry for others (Intel Foundry Services), but historically it’s been IDM-focused. • How it works: Intel designs CPUs, GPUs, and other chips → manufactures them in Intel’s own fabs → sells them directly to PC makers, server OEMs, and cloud companies. • Revenue source: Sale of finished chips (design + manufacturing margin). • Risk profile: If a design fails or demand drops, Intel bears both the design and manufacturing losses. Example: Intel designs the Core i9 CPU → manufactures it in its own fabs → sells to Dell, HP, Lenovo, or directly to consumers. If the Core i9 has performance issues, Intel not only loses manufacturing money but also faces brand damage and unsold inventory. ⸻ Quick Analogy: Think of TSMC as a printing press that prints books for many authors — it doesn’t write the books, just prints them. Intel is like an author who owns their own printing press — writes the book and prints it themselves, and sometimes now offers printing services to other authors. ~~~~~~ If you are looking to invest in semiconductors, and need expert insights, drop us a DM.

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VLSI is categorised into many different subfields but primarily into Frontend and Backend. Considering Frontend, there are certain roles that a RTL and a Verification engineer has to pursue through out one's career. Below are some of the specific roles: [1] RTL Design Engineer: Mostly deals with the HDL coding and designing of various modules, blocks using VHDL/Verilog/SV and to make sure the design is synthesizable. Also deals with CDC analysis, Safety modules, lint and superlint, power and area estimation, etc [2] IP/SOC Design Engineer: The role is same as discussed above, only difference is with the blocks and Modules. IP is a basic building block of the design and the role of IP designer is to code the functionality of the IP. The role of SOC designer is to check whether all the IP's are integrated and write the code for Top level design. [3] RTL Integration Engineer: They mostly deals with the integration of different blocks, interconnection of signals, porting of module. [4] IP/Subsystem Verification Engineer: a. UVM/OVM based Verification Environment creation for IP or a subsystem. b. Creating Verification and Test Plan, Assertion Plan c. Writing Testcases ( Directed, Random, Stress, Corner) in SV or UVM to verify the features. d. Coverage closure and Regression Management, debugging Testcases, Proper Verification, CDC Verification. [5] Formal Verification Engineer: Model Checking, Register Verification, Exhaustive verification of blocks, RTL Equivalence checks, Algorithmic and Arithmetic Verification, Connectivity checks. [6] Power Aware Verification(UPF): Power domain, level shifter, Voltage domain, Power gating, Power estimation. [7] Safety Verification: FMEDA analysis, Calculating Diagnostic Coverage, Fault Injection in Simulation and Emulation, Fault analysis, Calculating Fault metric. a. Single point Fault. b. Multi point Fault c. Latent Fault. ☆ Verification of Safety mechanism ( ECC, MECC, Parity, etc) [8] SOC Verification Engineer: a. Integrating multiple IP's b. Connectivity Checks. c. C based Testcases d. Booting Sequence. e. Data Path Verification. f. Processor Verification. #vlsi #asic #electricalengineering #engineering

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Today I saw something truly impressive. A first-time Physical Design student — no prior routing or LEF/DEF experience — cracked a problem that even experienced engineers struggle with. A net refused to route. Halos increased, layers adjusted, congestion relaxed… nothing worked. Instead of giving up, the student inspected the macro LEF and found the real culprit: a tiny M4 OBS blockage sitting exactly on the OUT pin, making it impossible for the router to legally access the pin. For a newcomer to spot a pin-access obstruction on Day 1 — that’s real engineering intuition. This is the mindset the industry needs: not just running the flow, but understanding why it breaks. If you want to build this kind of problem-solving ability, the Digital VLSI SoC Design & Planning workshop is designed exactly for that. https://lnkd.in/gSxH-pQR Real issues. Real debugging. Real growth.

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🔍 What NOT to Do in Interviews Over the past couple of months, I’ve averaged more than one interview per day — across roles in Silicon Design, including RTL Design, DV, DFT, Physical Design, Test, and Validation. After speaking with so many candidates, I’ve noticed a few consistent worst practices that tend to derail otherwise promising interviews — and, more importantly, what they reveal about a candidate’s mindset. Here are the common red flags I’ve observed: 1. Long and Irrelevant Introductions Candidates often go off-track with lengthy intros, listing every tool and technology they’ve ever touched — but with no relevance to the role. ✅ Keep it sharp and role-focused. 2. Not Listening (Even When Hints Are Given) When an interviewer nudges you in the right direction and you ignore it, that’s a missed opportunity. ✅ Interviews are collaborative, not adversarial. 3. Resumé ≠ Reality If it’s on your resumé, be ready to go deep. ✅ Substance matters more than style. 4. Refusing to Say “I Don’t Know” Trying to bluff through a technical question never ends well. ✅ It’s okay not to know — show how you’d find out. 5. Poor Communication of Thought Process Getting the right answer is great — but we also need to understand how you got there. ✅ Think out loud. 6. Taking Full Credit for Team Achievements It’s important to clarify your individual contribution. ✅ Own your impact, but give credit where it’s due. 💡 My Biggest Takeaway? Attitude > Aptitude You can coach someone to fill a knowledge gap, but you can’t teach curiosity, humility, or the ability to listen. Aptitude is trainable. Attitude often isn’t. 👉 If you're a candidate prepping for interviews, hope this helps. #InterviewTips #ASIC #Hiring #CareerGrowth #Mindset

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Chip Validation is Broken—And It's Costing the Industry Billions NVIDIA ($2T market cap), Intel ($150B+), AMD ($300B) — all pushing the limits of chip design. But nobody’s talking about the hidden bottleneck slowing their progress: Validation inefficiencies that delay launches and burn resources. These aren’t isolated issues. They’re systemic failures. Before a chip hits the market, it undergoes extensive testing to ensure it performs as expected under real-world conditions. This process—chip validation—is crucial for verifying functionality, performance, and reliability. But validation today is painfully slow. Engineers spend weeks scripting and running tests manually, dealing with fragmented tools, and sifting through scattered data to debug issues. The result? Delays, inefficiencies, and skyrocketing costs. The Broken Playbook -Weeks spent scripting tests instead of analyzing results -Scattered data across tools, slowing debugging cycles -Manual processes introducing errors and inefficiencies Behind the cutting-edge innovation lies a brutal truth: Validation is stuck in the past the last software that was built for validation released in 2001 (LabView). The Future of Validation: A new era is emerging: Automated, AI-driven validation workflows. And the results are game-changing: 20x faster test execution Fewer errors, more actionable insights Seamless collaboration across teams At Atoms, we’re not just talking about the future—we’re building it: One platform to automate and accelerate chip validation AI-assisted workflows/Analytics to streamline debugging Real-time insights for faster decision-making Because while traditional validation burns months, the companies of the future are already moving at light speed. The old methods had their time. The age of AI-powered validation has begun. #Semiconductors #ChipValidation #FasterTimeToMarket #TestFlow

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99% of silicon verification engineers I’ve worked with across high-performance teams had this one habit that made them stand out: → They never underestimated CDC issues. They always prioritized CDC verification early and often. In multi-clock designs, CDC bugs are silent killers. They don’t show up in functional simulations. But they do show up in silicon—when it’s too late. CDC verification trumps post-silicon debugging, every single time: 1. A clean CDC report > A clean simulation run Because simulation won’t catch metastability or data loss across domains. 2. One async FIFO test > Endless waveform reviews You’ll find glitches, data corruption, and missed handshakes in minutes. 3. “Let’s run CDC lint” > “Let’s wait for integration” Early CDC checks save weeks of rework and painful root cause analysis. 4. One-day CDC tool run > Month-long debug cycles Tools like SpyGlass, Questa CDC, or VC CDC give instant feedback on risky crossings. 5. Even a flagged false positive > A missed real bug Because every CDC warning is a chance to learn, align, and improve design intent. The best DV engineers get this: → CDC isn’t just a checklist item. It’s a mindset. It’s about designing with clarity, verifying with rigor, and preventing the silent bugs that cost millions. CDC issues don’t shout. They whisper. And the best engineers are the ones who listen early. Have you faced CDC issues in your verification? Do let me know what do you think and have you heard about it? Comment down 👇🏻👇🏻 Like, comment and follow Jatin Koshiya to see more content like this. #cdc #dv #asyncfifo #verification #hiring #usa #ushiring #vlsijobs #mentor #jatinkoshiya

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