ROHITH ANNABATHULA’s Post

The companies that built the semiconductor industry didn't start as giants. ASML started in a shed behind a Philips factory in 1984. KLA was founded by two engineers with a rented office and a borrowed oscilloscope. Lam Research started with one etch tool and a dream. Right now, in 2026, the next generation of semiconductor tool companies is raising money and building the machines that will define the next decade of chip manufacturing. Here's who's making waves — and where they're from: 🇳🇴 NORWAY — Lace Lithography ($40M Series A) Helium atom beam lithography with a claimed 0.1nm beam width. If it works, it could challenge EUV for certain applications. Founded 2023. Target: pilot fab tool by 2029. 🇨🇭 SWITZERLAND — Chiral ($12M Seed, ETH Zurich spin-out) Robotic nanomaterial integration and metrology for carbon nanotube transistors. Wafer-scale fabrication of next-generation transistors. The materials science play nobody is talking about. 🇨🇦 CANADA — Femtum ($11.8M Series A) Mid-infrared fiber laser platform for semiconductor equipment — laser cleaning and trimming at wafer level. The precision laser tool company fabs will need as features shrink below 2nm. 🇯🇵 JAPAN — Gaianixx ($12.7M Series C) Epitaxy technology for growing high-quality single crystals using dynamic lattice matching. University of Tokyo spin-out. Applications in power devices, MEMS, and LEDs. Backed by JX Metals, Toray, and Mitsui. 🇯🇵 JAPAN — Photo electron Soul ($5.6M Venture) Equipment startup. Minimal public disclosure — which in Japan usually means the technology is serious and the IP is protected. 🇺🇸 USA — ThirdAI Automation ($3M Seed) AI-powered root cause analysis for semiconductor equipment failures. Unifies equipment logs, sensor streams, images, and service reports into a causal intelligence layer. The 5 Why's, automated. Founded 2024. 🇧🇪 BELGIUM — Vertical Compute ($42.9M Seed, imec spin-off) 3D memory + compute chiplet architecture for AI hardware. Stores bits in high-aspect-ratio vertical structures with computation units directly below. The memory wall solution. --- The next wave of semiconductor innovation is NOT coming from the US alone. It's coming from Norway, Switzerland, Canada, Japan, Belgium — simultaneously. The CHIPS Act created urgency. That urgency created capital. That capital is now funding tools that didn't exist 3 years ago. The companies that hire the technicians who run these tools will be the ones who win the next decade. Which of these startups are you watching? #CleanroomTimes #Semiconductor #SemiconductorEquipment #StartupFunding #EUV #Lithography #FabTech #Cleanroom #SemiconductorIndustry #Innovation

It’s Not Just Machines; It’s the "Human Silicon" 🧠🤝 (Part 3/6) You can buy the best lithography scanners in the world, but without the right team, they are just expensive sculptures. In 2026, the global semiconductor talent war has reached a fever pitch. We aren't just looking for "workers"; we are looking for specialists who can operate at the intersection of physics, chemistry, and extreme precision. 🚀 The Workforce Reality: 1 Million Strong by 2030 According to the India Decoding Jobs 2026 Report, the Indian semiconductor sector alone is projected to employ 220,000 professionals by FY 2026. Across the broader ecosystem—from R&D to the cleanroom floor—we will need nearly one million skilled hands by the end of the decade. 🚀 The "Skill Stack": Diversity of Expertise A semiconductor plant is a high-stakes symphony that requires different "instruments" depending on the facility type: 🚀 Front-End Logic & Memory (The Scientists): Requires PhDs and Master’s degrees in Material Science and VLSI. These teams manage Yield Engineering—where a 1% improvement can save $100M annually. They oversee processes like Atomic Layer Deposition (ALD) and Extreme Ultraviolet (EUV) lithography. 🚀 Compound Semiconductor Fabs (The Power Specialists): These teams focus on "Wide Bandgap" materials like SiC and GaN. Their expertise is in high-voltage robustness and thermal management—critical for the 2026 EV and 6G infrastructure boom. 🚀 ATMP & OSAT (The Precision Ops): Assembly, Testing, Marking, and Packaging is where the "Human Silicon" meets automation. With the rise of 3D Packaging and Chiplets, roles in Wire Bonding and Die Attach have evolved into high-tech automation management. 🚀 The Support Pillars: We often forget the Facility Engineers. They manage the Ultra-Pure Water (UPW) systems and Class 1 to Class 100 cleanroom environments where even a speck of dust is a "catastrophic event." 🚀 Bridging the Gap: 2026 Training Modules The shortage of "fab-ready" talent is being met with unprecedented local initiatives: 🚀 AI-Enhanced Learning: Gamified training modules and AR/VR simulations are now being used to train non-experts on complex equipment like PVDF wet benches without risking actual hardware. 🚀 Strategic Academic Hubs: Institutions like IISc (CeNSE) and the IITs have launched "Semiconductor Workshops" to fast-track engineers into industry-ready roles. 🚀 Global Knowledge Transfer: We are seeing a "Reverse Brain Drain" where Indian expats from global hubs are returning to lead greenfield projects in Dholera and Sanand. Which role do you think is the hardest to fill in 2026: The PhD in the lab or the Technician in the cleanroom? Let’s debate below. 👇 #SemiconductorJobs #WorkforceDevelopment #SkillIndia #DeepTech #HumanSilicon #SemiconIndia2026 ~~~~ If you are looking to invest in semiconductors and need expert solutions, drop us a DM. Link in comments.

One Dutch company controls who wins the AI race. ASML. They make the only machines on Earth capable of printing chips at 2–3 nanometer scale. Extreme ultraviolet lithography. One company. No real alternative. Full stop. China has the capital. The engineers. The national will. The subsidies. What they don't have: the machine. ASML is the sole producer of the EUV lithography machines needed to make the most advanced chips. And they've never sold a single EUV machine to a Chinese customer. But here's what most people miss. This isn't just a trade war story. It's a physics story. Building a better lithography machine isn't a manufacturing problem you throw money at. It requires solving engineering problems at the intersection of plasma physics, optics, and precision mechanics — simultaneously. Elon Musk's proposed "TeraFab," designed to scale AI compute to the terawatt level, starts with ASML hardware. Not because he wants to. Because there's no other option yet. China reportedly built a prototype EUV system — but it won't reach commercial viability until 2030 at the earliest. Meanwhile, China's best demonstrated domestic lithography tools are only 28nm-capable, and even those don't appear to be in mass production. The entire global frontier of AI compute runs through one factory in Veldhoven, Netherlands. That's not a bottleneck. That's a chokepoint with a moat made of physics. Which technology chokepoint worries you most for the next decade? #Semiconductors #AI #Geopolitics #ChipWar #ASML

A great example on developments dominated in the beginning by reactions of “unlikely or impossible” but which in time with innovations and engineering stamina slowly turn into “logical” developments.

The Silicon Stack (2/?) Not all power is visible. Some of it is printed. Layer by atomic layer. We thought software ate the world. Turns out -- silicon did. No chips > no AI No AI > no edge No edge > no sovereignty Simple. Brutal. Non-negotiable. A $400M machine Printing shadows of light At 13.5 nanometers One company builds it. A handful can use it. Everyone else negotiates. This isn’t supply chain. This is choke chain. Lithography. Logic. Packaging. त्रयम् -- the new trinity of power. And somewhere in this stack India is quietly choosing where to enter the game. Not at the top. Not yet. But exactly where the future bottleneck lives. Because in 2026 -- It’s not the transistor that wins. It’s how you connect them. For the full slide deck see my blog post https://lnkd.in/gWruPFYp #Geopolitics #Semiconductors #AI #India #Yantrajaal #TechPower #PraxisBusinessSchool

There is a recurring assumption in global technology policy: If enough capital, talent, and intent are deployed, any monopoly can be challenged.EUV lithography disproves that assumption. ASML is not just ahead. It operates in a zone where competition is constrained by physics, economics, and accumulated learning. Start with the nature of the system. EUV is not a single product. It is a tightly coupled stack of extreme precision components—plasma light sources, ultra-flat mirrors, vacuum systems, and nanoscale alignment. Critical subsystems like mirrors are supplied by ZEISS Group, with tolerances measured at atomic levels. Each layer must perform flawlessly, in synchrony, at industrial scale. This is not engineering difficulty alone. It is integration difficulty at the edge of physical limits. Now consider economics. ASML ships roughly 40–50 EUV systems annually, each priced north of $200M. That volume is paradoxical—too small for a challenger to amortize multi-decade R&D, yet too critical for leading fabs to risk switching. This creates a structural lock-in. Unlike software, where marginal cost trends to zero, EUV operates in a regime where marginal cost remains high and learning curves are slow. The entry barrier is not just capital; it is time. Time compounded over decades. Operating data becomes the real moat.EUV machines run continuously in advanced fabs. Over years, ASML has accumulated millions of hours of performance data—failure modes, calibration cycles, yield optimization patterns. This dataset is not publicly available, nor easily reproducible. A new entrant does not just need to build a machine. It must replicate a decade of real-world learning—without customers willing to tolerate downtime. History reinforces this. Japan’s Nikon and Canon Inc. had both capability and capital. Yet both exited EUV more than a decade ago. Not due to lack of talent, but because the equation did not close—technically or economically. Policy has limits. China has treated semiconductor self-sufficiency as a national priority, deploying significant capital into domestic tooling. Yet EUV remains out of reach. This is not a funding gap. It is a technology stack gap compounded over time. What does this mean strategically? First, not all monopolies are market failures. Some are outcomes of extreme specialization and cumulative advantage. Second, industrial policy cannot shortcut physics. It can accelerate adoption, but not compress foundational discovery cycles beyond a point. Third, control in semiconductors is shifting upstream—from chips to the tools that make chips. ASML sits at a leverage point where a small number of systems influence the output of the entire advanced node ecosystem. Fourth, supply chains are becoming less substitutable. In EUV, there is no “Plan B” vendor. That changes how risk, geopolitics, and alliances are structured. The deeper insight is this: contd in comments... DC* Dinwins

🏆 𝑻𝒓𝒂𝒏𝒔𝒇𝒐𝒓𝒎𝒊𝒏𝒈 𝑺𝒆𝒎𝒊𝒄𝒐𝒏𝒅𝒖𝒄𝒕𝒐𝒓 𝑰𝒏𝒏𝒐𝒗𝒂𝒕𝒊𝒐𝒏: 𝑨𝒅𝒗𝒂𝒏𝒄𝒆𝒅 𝑷𝒂𝒄𝒌𝒂𝒈𝒊𝒏𝒈 𝑳𝒊𝒕𝒉𝒐𝒈𝒓𝒂𝒑𝒉𝒚 𝑬𝒒𝒖𝒊𝒑𝒎𝒆𝒏𝒕 𝑴𝒂𝒓𝒌𝒆𝒕 🔬⚙️ 📊 𝑴𝒂𝒓𝒌𝒆𝒕 𝑺𝒊𝒛𝒆 & 𝑭𝒐𝒓𝒆𝒄𝒂𝒔𝒕 The Advanced Packaging Lithography Equipment Market is projected to grow from USD 2.6 Billion in 2025 to USD 5.4 Billion by 2032, registering a CAGR of 11.0% during the forecast period 📈 ➢ 🔽 𝑨𝒄𝒄𝒆𝒔𝒔 𝒕𝒉𝒆 𝑷𝑫𝑭 𝑺𝒂𝒎𝒑𝒍𝒆 𝑹𝒆𝒑𝒐𝒓𝒕 𝒘𝒊𝒕𝒉 𝑶𝒏𝒆 𝑪𝒍𝒊𝒄𝒌 📊 https://lnkd.in/dHwx_Dr8 📊 𝑲𝒆𝒚 𝑴𝒂𝒓𝒌𝒆𝒕 𝑫𝒓𝒊𝒗𝒆𝒓𝒔 & 𝑰𝒏𝒔𝒊𝒈𝒉𝒕𝒔 💡 Rising demand for high-performance computing & AI chips 📦 Growth of advanced packaging (2.5D/3D IC, fan-out) ⚡ Increasing need for miniaturization & high-density integration 🚗 Expansion of automotive electronics & EVs 📡 Rapid deployment of 5G infrastructure 📊 𝑴𝒂𝒓𝒌𝒆𝒕 𝑺𝒆𝒈𝒎𝒆𝒏𝒕𝒂𝒕𝒊𝒐𝒏 🔽 By Type : 🔬 Advanced Lithography Equipment ⚙️ Mask Aligners & Steppers 🔽 By Application : 📱 Consumer Electronics 🚗 Automotive 💻 IT & Telecom 🏭 Industrial 🔽 By Packaging Technology : 📦 Fan-Out Wafer Level Packaging (FOWLP) 🧩 2.5D/3D IC Packaging 🔗 System-in-Package (SiP) 🏆 𝑻𝒐𝒑 𝟒𝟎 𝑲𝒆𝒚 𝑷𝒍𝒂𝒚𝒆𝒓𝒔 ➡️ ➣ ASML ➣ Nikon Precision Inc. ➣ Canonical ➣ Applied Materials ➣ Tokyo Electron ➣ KLA ➣ Lam Research ➣ SCREEN Semiconductor Solutions Co., Ltd. ➣ Veeco Instruments S.A.S. ➣ SUSS MICROTEC LTD. ➣ The EV Group (EVG) ➣ Onto Innovation ➣ Kulicke & Soffa ➣ ASM International ➣ Hitachi High-Tech Corporation ➣ Advantest ➣ Teradyne ➣ DISCO ➣ ULVAC Technologies, Inc. ➣ Shibaura Mechatronics Corp ➣ ZEISS Semiconductor Manufacturing Technology ➣ Rudolph Technologies ➣ FormFactor Inc. ➣ Technoprobe ➣ Amkor Technology, Inc. ➣ ASE Group ➣ JCET Group ➣ Powertech Technology (Suzhou) Ltd. ➣ TSMC ➣ Samsung Electronics ➣ Intel ➣ SK hynix ➣ Micron Technology ➣ GlobalFoundries ➣ SMIC ➣ UMC ➣ Infineon Technologies ➣ STMicroelectronics ➣ NXP Semiconductors ➣ Renesas Electronics 📊 𝑻𝒐𝒑 𝑻𝒓𝒆𝒏𝒅𝒔 𝑺𝒉𝒂𝒑𝒊𝒏𝒈 𝑻𝒉𝒆 𝑴𝒂𝒓𝒌𝒆𝒕 🚀 Shift toward EUV & advanced lithography nodes 📦 Rapid adoption of heterogeneous integration 🤖 AI-driven semiconductor manufacturing ⚡ Growth in chiplet-based architectures 🌐 Expansion of global semiconductor fabs 📊 𝑾𝒉𝒚 𝑻𝒉𝒊𝒔 𝑴𝒂𝒓𝒌𝒆𝒕 𝑴𝒂𝒕𝒕𝒆𝒓𝒔 ✔️ Enables next-gen semiconductor packaging ✔️ Supports high-speed, low-power devices ✔️ Critical for AI, 5G, and EV innovation ✔️ Drives performance and miniaturization #️⃣ #Semiconductor #Lithography #AdvancedPackaging #ChipManufacturing #AI #5G #EV #Electronics #Innovation #TechTrends #Microelectronics 🚀🔬

This article delves into the fascinating world of lithography, the intricate manufacturing process that enables the production of semiconductor chips. I found it interesting that the level of precision required for chip-making is on par with drawing patterns smaller than a virus! As the tech landscape evolves, I wonder what innovations will emerge from the next wave of semiconductor startups. What are your thoughts on the future of semiconductor technology?

I didn’t expect an Indian startup to make me look at the lithography, but SemiLit is worth a closer read. It touches the core of chipmaking. The company says it’s building a DUV immersion lithography tool (deep ultraviolet light using liquid between lens and wafer to print tiny circuits) aimed at the 28nm class. Target throughput is ~310 wafers per hour. And it’s priced far below today’s market leaders. Because 28nm is still everywhere in the real world e.g. automotive, industrial systems, analog chips. Not cutting edge, but very important. The chips on which Infineon, Nexperia, and NXP have built their empires. China is moving in the same direction, as I shared in my post earlier. SMIC is testing a domestically built immersion DUV system from Yuliangsheng, also targeting 28nm-class production. Same idea: replace imported lithography tools like ASML’s machines with local alternatives. Beijing’s direction is pretty clear. Reduce dependence, build full-stack control. What’s forming isn’t a simple “ASML vs everyone else” story but multiple regions trying to crack the same middle layer of chip production. Not EUV (extreme ultraviolet for cutting-edge chips), but the "boring" DUV layer that still runs a huge chunk of global manufacturing. India with SemiLit. China with SMEE-linked efforts and partners like Yuliangsheng. Others quietly circling the same problem. Same same, bottleneck but different flags. But here’s the part that actually decides everything. The real test is never throughput or node claims alone. I read that overlay accuracy (how precisely layers align), uptime, serviceability, defect rates, and full fab qualification decide whether a tool survives in production. That’s the nuance in lithography. ASML still sits as the global benchmark for a reason. And that ecosystem is the hard part to replicate. Not just machines but the entire reliability stack. If the economics really work out, it changes who can realistically build chip capacity and where. That becomes a geopolitical lever. Right now, SemiLit and China’s DUV efforts look less like replacements and more like new competitive pressure points. But they are exactly the kind of pressure that reshapes the "good enough" layer of global manufacturing over time. Slowly, then suddenly. Boring chips are strategic. #Semiconductors #Lithography #SupplyChain #ASML #India #China Source: Eveosian on X

Repairing Chips Atom by Atom Semiconductor manufacturing has always advanced by subtraction. To make a circuit smaller, material must be removed more precisely than before. For decades, the governing metaphor of progress was lithography: https://lnkd.in/dypcXv3v