FPGAs Power Space Applications with Capella Space

Takes me back to when I was a EE student in college and we set up kinds of circuits on our breadboards... To those that are interested in learning about what powers most next-generation in-space processing, this article from Capella Space is a great informative summary. Side note: as a recruiter in the Space industry, I have seen a clear pattern — FPGA engineers are incredibly in-demand. To the engineering-inclined college students out there: take a look at studying this!

I’m excited to share that my paper is published at the 2025 9th International Conference on Recent Advances and Innovations in Engineering (ICRAIE 2025): “An SPI-Driven FPGA Platform for Multi-Parameter Data Acquisition and Logging in Satellite Applications.” Reliable telemetry is critical for satellite subsystems, especially when monitoring power and thermal behavior. In this work, we focus on capturing and logging key electrical parameters including voltage, current, and temperature, enabling clearer visibility into subsystem performance and supporting health monitoring, validation, and post-test analysis. The platform was implemented and tested, demonstrating accurate and efficient performance. DOI: https://lnkd.in/dTZbn9hJ #ICRAIE2025 #Satellite #SpaceSystems #Telemetry #AerospaceEngineering #EmbeddedSystems #EngineeringResearch #FPGA

The major milestone of 2011 was the release of GR712RC prototype device. The introduction of this dual-core LEON3FT-based microprocessor enabled spacecraft computers to handle more complex workloads with reliability. This prototype laid the foundation for flight models that would later power missions from launchers to deep space. The GR712RC was taped-out on Tower Semiconductor’s 180 nm CMOS process utilizing a rad-hard library. Simultaneously, the GR712RC-BOARD evaluation board was introduced as a platform to support early software development and testing. This evaluation board provided engineers with a practical environment to validate software, assess performance, and accelerate integration. One of our best sellers! The year also marked the launch of the RT-SPW-ROUTER, a standard product consisting of a radiation tolerant SpaceWire routing switch with up to 10 ports and with PCI support, all implemented on the RTAX2000S FPGA technology and offered as a preprogrammed off-the-shelf product. The GR703 CCSDS TM/TC Chip was also implemented on RTAX2000S FPGA technology offering a complete Telemetry encoder and Telecommand decoder system together with SpaceWire links and PCI support, all based on IP cores from our own GLIB library. Learn more about the GR712RC: https://lnkd.in/gWvGNnYG #Gaisler25YearsInSpace #SpaceComputing #gr712rc

Quantum computers are often presented as a single technology, but in practice there are very different architectural approaches. Today, two of the most prominent are ion trap and superconducting qubits—each with clear strengths and trade-offs. In ion trap architectures, qubits are individual atoms confined in space by electromagnetic fields. They offer very long coherence times, high gate fidelity, and near all-to-all connectivity between qubits. The challenge lies in scalability: laser control, synchronization, and system complexity grow rapidly, pushing the field toward modular architectures connected via photonic interconnects. Superconducting qubits, on the other hand, are fabricated as circuits on chips and operate at extreme cryogenic temperatures. Their key advantage is compatibility with industrial fabrication and fast gate speeds, enabling rapid scaling in qubit count. The downside is higher error rates and shorter coherence times, making Quantum Error Correction (QEC) absolutely central. In the end, it’s not about “which is better,” but which architecture can scale reliably. The quantum race will be won by mastering classical integration, real-time control, and systems engineering—not just qubits. #QuantumComputing #IonTrap #SuperconductingQubits #QuantumArchitecture #QEC #DeepTech #FutureOfComputing

A new Nature Communications study presents a chip-scale quantum emitter that can dynamically reconfigure photon lifetimes without sacrificing brightness—an ability long considered unattainable in integrated photonics. Schumpeter’s latest analysis explains how a PT-symmetric dual-ring microresonator on silicon nitride allows lifetime tuning over a twenty-fold range while preserving high pair-generation efficiency, enabling a single device to serve both long-haul quantum communication (narrow linewidths for memory coupling) and high-speed processing (broad bandwidths for fast operations). The report details the Exceptional-Point physics behind the tuning mechanism, the implications for programmable quantum networks, and the engineering barriers that must be overcome before industrial deployment. For quantum-network architects, telecom operators and semiconductor manufacturers, this technology signals the emergence of adaptive, CMOS-compatible quantum light sources capable of bridging heterogeneous architectures across the future quantum internet. Full analysis available to Schumpeter subscribers. #Schumpeter #QuantumPhotonics #PTsymmetry #ExceptionalPoint #SiliconNitride #QuantumNetworks #QuantumInternet #IntegratedPhotonics #QuantumEmitters #NonHermitianPhysics #DeepTech #FrontierScience https://lnkd.in/dmwMPE22

𝗤𝘂𝗮𝗻𝘁𝘂𝗺 𝘁𝗿𝗮𝗻𝘀𝗶𝘀𝘁𝗼𝗿𝘀 𝗰𝗼𝘂𝗹𝗱 𝗯𝗲 𝘁𝗵𝗲 𝗯𝗿𝗲𝗮𝗸𝘁𝗵𝗿𝗼𝘂𝗴𝗵 𝘁𝗵𝗮𝘁 𝗯𝗿𝗶𝗱𝗴𝗲𝘀 𝗰𝗹𝗮𝘀𝘀𝗶𝗰𝗮𝗹 𝗲𝗹𝗲𝗰𝘁𝗿𝗼𝗻𝗶𝗰𝘀 𝗮𝗻𝗱 𝘀𝗰𝗮𝗹𝗮𝗯𝗹𝗲 𝗾𝘂𝗮𝗻𝘁𝘂𝗺 𝗵𝗮𝗿𝗱𝘄𝗮𝗿𝗲. Recent advances in Quantum Transistors demonstrate how quantum effects can be controlled, switched, and amplified in a transistor-like manner - a long-standing challenge in quantum hardware engineering. Rather than replacing CMOS, quantum transistors enable hybrid quantum–classical architectures: on-chip control, tighter integration, and system designs that align with real semiconductor manufacturing constraints. This is not just a new device - it’s a new architectural path for taking quantum systems from fragile lab setups to industrial-scale hardware. #QuantumHardware #QuantumTransistors #Semiconductors #QuantumElectronics #DeepTech #FutureOfComputing

🔬 Quantum Chip Under Development I’m currently working on a next-generation quantum hardware concept leveraging long-coherence qubits and chip-integrated control systems. The goal is to explore architectures that push beyond the limitations of current quantum platforms — focusing on stability, scalability, and precision at the hardware level. Early design work has included: • Hybrid qubit strategies for robust quantum memory • Advanced trap-based chip structures • Novel control pathways for high-fidelity logic It’s still in the research and modeling stage, but the outlook is promising. Innovation often begins by challenging existing assumptions — and I’m excited to continue expanding what quantum processors can achieve. More updates as the project evolves. 🚀 #QuantumComputing #QuantumHardware #DeepTech #LongCoherenceQubits #EmergingTech #ResearchInnovation

⚛️ 𝗙𝗮𝘂𝗹𝘁-𝘁𝗼𝗹𝗲𝗿𝗮𝗻𝘁 𝗾𝘂𝗮𝗻𝘁𝘂𝗺 𝗰𝗼𝗺𝗽𝘂𝘁𝗶𝗻𝗴 𝗺𝗼𝘃𝗲𝘀 𝗶𝗻𝘁𝗼 𝘀𝘆𝘀𝘁𝗲𝗺 𝗲𝗻𝗴𝗶𝗻𝗲𝗲𝗿𝗶𝗻𝗴 A new report by Quantum Source defines concrete engineering pathways toward fault-tolerant quantum systems across superconducting, ion-trap, neutral-atom, photonic and spin qubits. 🧩 Error correction is treated as a full system problem: control electronics, calibration, timing stability, cryogenics and yield. 📈 Logical qubits surpass physical qubits in selected experiments, enabling longer and more reliable circuits. 🔌 Scaling shifts toward integration challenges: interconnects, chip coupling, thermal design and classical-quantum co-design.  The field is moving from qubit counts to runtime stability and system reliability. For more insights: https://lnkd.in/da-Hfkgz  Jorge Thomas // George Gesek // Alessandro Ricci, PhD // Anne-Catherine de la Hamette // Dr. Ivan Sergeev

Pleased to share our recent publication in AVS Quantum Science with #ProfBermak, presenting a fully integrated 45 nm CMOS system-on-chip receiver designed for the readout of transmon qubits. This work integrates quantum device modeling, Josephson parametric amplification, and advanced CMOS RF design to enable reliable detection of ultra-low-level quantum signals. The study delivers a compact, low-noise, wideband receiver architecture capable of supporting large-scale qubit readout, advancing the pathway toward scalable quantum computing hardware. #Transmon, #45nmCMOS, #RF, #SoC, #LNA, #IF, #Mixer

From "Lab Routing" to "On-Chip Control": On-chip control combined with multiplexing significantly reduces the number of cables required to control a large number of qubits. Transferable Control Architecture: This control technology, validated in its annealing system (controlling a large number of qubits/couplers with fewer bias lines), is now being extended to the gate model route, pointing to a more realistic scalable architecture. Advanced Packaging in Place: Multi-chip packaging integrates the highly coherent fluxonium qubit chip with a multi-layer control chip, employing superconducting bump bonding and low-temperature packaging processes. Next Steps: Qubits 2026 on January 27-28 will reveal more roadmaps and progress. I look forward to seeing more systematic metrics and scalability pathways (yield, thermal budget, crosstalk, manufacturability, etc.). The long-term competition in quantum computing ultimately boils down to one question: Who can transform "physically feasible" into "engineerably manufacturable + scalable delivery"? What combination of technologies do you think will drive the scalability inflection point of the gate model first? #QuantumComputing #GateModel #Cryogenics #AdvancedPackaging #SuperconductingQubits #Fluxonium #SemiconductorManufacturing #HardwareEngineering #DWave #QBTS #Qubits2026