Paper Published: SPI-Driven FPGA Platform for Satellite Telemetry

Takes me back to when I was a EE student in college and we set up kinds of circuits on our breadboards... To those that are interested in learning about what powers most next-generation in-space processing, this article from Capella Space is a great informative summary. Side note: as a recruiter in the Space industry, I have seen a clear pattern — FPGA engineers are incredibly in-demand. To the engineering-inclined college students out there: take a look at studying this!

While quantum algorithms and qubit stability rightfully capture significant attention, the sophisticated classical control infrastructure underpinning quantum computers presents an equally formidable engineering challenge for hardcore developers. Achieving reliable quantum operations necessitates classical control systems capable of nanosecond-level synchronization and ultra-low latency signal delivery. These bespoke systems, often built on high-speed FPGAs and custom electronics, are responsible for precise qubit manipulation—a timing deviation of even a few nanoseconds can critically compromise quantum coherence. This demands deep expertise in real-time systems, signal processing, and high-performance embedded development. Understanding and mastering this complex classical-quantum interface is paramount for advancing scalable quantum architectures. What are your perspectives on the integration challenges between classical and quantum layers? #QuantumComputing #HardwareDevelopment #RealTimeSystems #DeepTech #QuantumEngineering #FPGA

High-speed ADC/DAC systems are at the core of applications such as software-defined radio, test & measurement, medical imaging, and industrial sensing, where deterministic latency and timing consistency are non-negotiable. This JESD204B implementation on Efinix, Inc. Titanium FPGA, demonstrated with Texas Instruments data converters and developed by Logic Fruit Technologies, is a solid example of moving from theory to measured, validated performance, including stable bring-up, synchronization, and deterministic latency. If you’re working on JESD204B-based ADC/DAC designs, check out more resources on the Efinix website. https://lnkd.in/gFnbW8uS #Efinix #FPGA #JESD204B #TI #AFE58 #DAC38

From "Lab Routing" to "On-Chip Control": On-chip control combined with multiplexing significantly reduces the number of cables required to control a large number of qubits. Transferable Control Architecture: This control technology, validated in its annealing system (controlling a large number of qubits/couplers with fewer bias lines), is now being extended to the gate model route, pointing to a more realistic scalable architecture. Advanced Packaging in Place: Multi-chip packaging integrates the highly coherent fluxonium qubit chip with a multi-layer control chip, employing superconducting bump bonding and low-temperature packaging processes. Next Steps: Qubits 2026 on January 27-28 will reveal more roadmaps and progress. I look forward to seeing more systematic metrics and scalability pathways (yield, thermal budget, crosstalk, manufacturability, etc.). The long-term competition in quantum computing ultimately boils down to one question: Who can transform "physically feasible" into "engineerably manufacturable + scalable delivery"? What combination of technologies do you think will drive the scalability inflection point of the gate model first? #QuantumComputing #GateModel #Cryogenics #AdvancedPackaging #SuperconductingQubits #Fluxonium #SemiconductorManufacturing #HardwareEngineering #DWave #QBTS #Qubits2026

#EthernetPhotonics integrates light-based (photonic) components directly with Ethernet networking, primarily using silicon photonics (SiPh) and Co-Packaged Optics (CPO) to overcome electrical signal limits, boosting power efficiency, density, and reliability for AI data centers by placing optical engines next to the switch ASIC, drastically cutting power and improving uptime for massive bandwidth needs. 

Even with the most advanced FPGA or RFSoC, analog filtering cannot be omitted. In long-term reliable and repeatable test and measurement systems, the analog front-end has always been a critical battlefield. The reasons are straightforward: Aliasing, overload, and nonlinear distortion, once introduced, directly affect the fidelity of the captured waveform. The strength of digital algorithms lies in precise processing and high repeatability across multiple measurements. However, algorithm implementations often assume that the signal under processing has not been severely corrupted. FPGA provides flexibility, consistency, and massive parallelism, but it cannot replace a properly designed analog front-end.

🔬 Quantum Chip Under Development I’m currently working on a next-generation quantum hardware concept leveraging long-coherence qubits and chip-integrated control systems. The goal is to explore architectures that push beyond the limitations of current quantum platforms — focusing on stability, scalability, and precision at the hardware level. Early design work has included: • Hybrid qubit strategies for robust quantum memory • Advanced trap-based chip structures • Novel control pathways for high-fidelity logic It’s still in the research and modeling stage, but the outlook is promising. Innovation often begins by challenging existing assumptions — and I’m excited to continue expanding what quantum processors can achieve. More updates as the project evolves. 🚀 #QuantumComputing #QuantumHardware #DeepTech #LongCoherenceQubits #EmergingTech #ResearchInnovation

This article provides accurate models of a circular wire loop antenna used for emission or reception. They are valid beyond the second series resonance where ka is close to 2. The article may be downloaded at https://lnkd.in/e9GU6r7V. This article and others are available in these LinkedIn groups: -the "Antennas and Propagation - Open Research" https://lnkd.in/eYGysf26 group; -the "Circuit Theory and Analog Electronics - Open Research" https://lnkd.in/e5swYV5r group; and -the "Electromagnetic compatibility (EMC) and signal integrity - Open Research" https://lnkd.in/evhE-DBv group. You are invited to join these groups! #Antenna #Loop #EMC

A major milestone in quantum error correction has emerged. Researchers have demonstrated fault-tolerant quantum error correction below the threshold using an all-microwave control approach on a 107-qubit superconducting processor. This marks a significant technical achievement and represents the first time a team outside the US has reached this benchmark. What makes this particularly noteworthy is the method itself. Traditional approaches to suppressing leakage errors rely on hardware-intensive techniques that add complexity to chip layouts and increase wiring demands inside the ultra-cold dilution refrigerators where quantum processors operate. As systems scale, routing more control lines into these environments becomes a serious engineering bottleneck. The new approach takes a different path. By using carefully timed microwave signals to keep qubits within their intended states and reset auxiliary qubits, the team achieved comparable results without the additional hardware overhead. The error-suppression factor of 1.4 confirms that the system is operating below threshold, meaning each increase in code size reduces logical errors rather than amplifying them. This matters for the broader industry because microwave control is already central to superconducting quantum computers. Extending that same layer to handle leakage suppression could simplify chip packaging, reduce wiring density, and ease the thermal constraints that challenge large cryogenic systems. We are still far from the hundreds of thousands of qubits needed for practical applications, but progress on multiple technical fronts continues to accelerate. #QuantumComputing #QuantumErrorCorrection #SuperconductingQubits #DeepTech #QuantumTechnology

We are happy to announce the keynote speaker for FDF26! 👉 Adam Taylor from Adiuvo Engineering & Training Ltd In his keynote, Adam will share his perspective on the impact of AI on FPGA engineering and discuss future trends shaping the industry. A must-see talk for anyone interested in how artificial intelligence is transforming FPGA design. Adam Taylor is a world recognised expert in design and development of embedded systems and FPGA’s for several end applications. Throughout his career, Adam has used FPGA’s to implement a wide variety of solutions from RADAR to safety critical control systems (SIL4) and satellite systems. He also had interesting stops in image processing and cryptography along the way.  Adam is Chartered Engineer, Senior Member of the IEEE, Fellow of the Institute of Engineering and Technology, he is also the owner of the engineering and consultancy company Adiuvo Engineering and Training which develops embedded solutions for high reliability, mission critical and space applications. FPGAs are Adam ‘s first love, he is the author of numerous blogs, articles papers and books on electronic design and FPGA design. 📅 Join us at CERN for FDF26: 27–29 May 2026 🔗 Learn more at: https://cern.ch/fdf26 The Call for Abstracts is still open until 28 February 2026. Don’t miss the chance to present your work and be part of the forum!