Tsu-Jae Liu

OpenAI and Cerebras have signed a multi-year agreement to deploy 750 megawatts of Cerebras wafer-scale systems to serve OpenAI customers. This has been a decade in the making. Deployment begins in early 2026, and when fully rolled out, it will be the largest high-speed AI inference deployment in the world. OpenAI and Cerebras were both founded in 2015 with radically ambitious goals. OpenAI set out to build the software that would push AI toward general intelligence. Cerebras set out to rethink computing hardware from first principles. Our teams met as far back as 2017. We shared ideas, early work, and a common belief: there would come a point when model scale and hardware architecture would have to converge. That point has arrived. ChatGPT set the direction for the entire industry. It showed the world what AI could be. Now we’re in the next phase - not proving capability, but delivering it at global scale. The history of technology is clear on one thing: speed drives adoption. The PC industry didn’t operate at kilohertz. The internet didn’t change the world on dial-up. AI is no different. As models grow more capable, speed becomes the bottleneck. Slow systems limit what users can do, how often they engage, and whether AI becomes infrastructure or remains a novelty. Cerebras was built for this moment. By keeping computation and memory on a single wafer-scale processor, we eliminate the data-movement penalties that dominate GPU systems. The result is up to 15× faster inference, without sacrificing model size or accuracy. That speed changes product design, user behavior, and ultimately productivity. For consumers, it means AI that feels instantaneous. For the economy, it means agents that can finally drive serious productivity growth. For Cerebras, 2026 will be a defining year. With this collaboration with OpenAI, Cerebras’ wafer-scale technology will reach hundreds of millions - and eventually billions - of users. We’re proud to work alongside OpenAI to bring fast, frontier AI to people around the world. This is what a decade of long-term thinking looks like.

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What’s the difference between 2.5D and 3D ICs? As Moore’s Law slows, the industry is shifting to system-level innovation—especially through advanced packaging. Two approaches lead the charge: 2.5D and 3D ICs. -> 2.5D ICs  Chips are placed side-by-side on a common interposer (silicon or glass), which routes connections between them.  Think of it as horizontal integration with higher bandwidth and lower latency than traditional PCBs. -> 3D ICs  Chips are stacked vertically and connected using TSVs (Through-Silicon Vias)—tiny vertical tunnels through silicon that shorten communication paths between layers. -> Analogy: 2.5D is like a city spread across one giant floor—buildings connected by roads. 3D is a skyscraper—floors stacked with elevators (TSVs) moving data vertically. Faster, denser, but harder to cool and build. 💡 Why it matters: These techniques help us move “beyond Moore” by: Increasing bandwidth Reducing latency Shrinking footprint Combining memory, logic, RF, and more in a single package -> Where it’s used: 2.5D: AMD GPUs, Xilinx FPGAs, HBM-connected AI accelerators 3D: Intel’s Foveros, Samsung HBM stacks, Apple M-series chips, and next-gen edge AI hardware Key takeaway:  It’s not just about smaller nodes anymore. Packaging is becoming the new performance lever—and how you connect dies matters as much as what you put on them. P.S. If you're looking for semiconductor news, and insights, check out our Blog The Semiconductor world—a guide to the chip industry in simple terms. Link in comments. #Semiconductors #AdvancedPackaging #2_5D #3DIC #HBM #AIChips #MooresLaw #SystemIntegration #TestFlow #ATOMS

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What is a PDK? PDK = Process Design Kit. It is a collection of files, models, and rules provided by a semiconductor foundry (TSMC, Samsung, Intel, GF, etc.) that describe how their fabrication process works. Think of it as the “bridge” between semiconductor manufacturing and chip design tools (EDA). • Foundry → defines the physics, materials, and device characteristics. • Designers → need this data inside CAD tools to create standard cells, IPs, and SoCs. • PDK = packaged knowledge of the process, usable in design flow. ⸻ What is inside a PDK? A PDK usually contains: 1. Design rules • DRC (Design Rule Check) – min width/spacing, enclosure, antenna rules, etc. • LVS (Layout vs. Schematic) – device recognition rules. • ERC/DFM checks. 2. Device models • SPICE models (transistors, diodes, resistors, capacitors). • Corner models (TT, SS, FF, SF, FS for process variations). • Parasitic models (RC extraction decks). 3. Technology files • Layer definitions (metal stack, vias, diffusion, poly). • Process stack information for layout tools. 4. Standard cell/IP views (sometimes included separately as a library) • Liberty (.lib) timing and power data. • LEF/DEF abstract views for PnR. • GDS/OASIS layout data. ⸻ Why is PDK useful for SoC/IP Design? When designing SoC or IP, you need to ensure your design is fabricatable in the target technology node (e.g., 5nm, 16nm, 28nm). PDK makes this possible by: 1. Accuracy in Simulation • Provides foundry-calibrated transistor models for SPICE/analog simulations. • Enables accurate timing, power, and noise simulations for digital flows. 2. Physical Verification • DRC/LVS decks ensure your layout follows foundry’s rules. • Prevents yield loss and fabrication errors. 3. Standardization • Ensures that all design teams (analog, digital, mixed-signal, IP vendors) work with the same process definitions. • Makes IP portable across SoC projects in the same technology node. 4. IP Integration • Provides abstract views for IP blocks (LEF/lib) so they can be cleanly integrated into SoC PnR. 5. Manufacturability & Yield • Includes DFM (Design for Manufacturability) rules. • Helps designers avoid systematic yield problems. ⸻ ✅ In short: A PDK is the recipe book for a semiconductor process. Without it, you can’t reliably design or tape out an SoC/IP. It ensures your design matches the physics of the foundry process and is manufacturable with good yield.

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Following TSMC’s exit in #GaN power device foundry services https://lnkd.in/gbHvE-rw , how the #industry will re-position and what will be the impacts? In this interview with Cem Basceri (CEO, Qromis, Inc.), we revisit the status and the facts in light of the media content specifically on Vanguard International Semiconductor Corporation (VIS), @ShinEtsu Chemical Co. Ltd., imec, QROMIS upon TSMC’s exit decision, and the status of GaN-on-QST commercial products and roadmaps as part of the GaN #power #industry evolution. #qst “There is no official statement from TSMC yet,” said Basceri. “But what we’re seeing now makes sense. GaN is still a young technology—mostly in generation one, with generation two emerging—and TSMC, while well-resourced, might have struggled to scale it profitably and meaningfully for consumer electronics markets which are being dominated by heavily subsidized Chinese players and at the same time faced transition challenges to large diameter #substrates along with performances beyond 650V with GaN-on-silicon platform. However, this is not the only reason.” Full Article: https://lnkd.in/gcfhzchj #powerelectronics #semiconductor #powerdesign #galliumnitride #siliconcarbide

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What is The Semiconductor Ecosystem: A breakdown for potential investment The semiconductor industry is a complex ecosystem with various players contributing to the creation of the chips that power our modern world. Here's a breakdown of the eight key types of companies: 1. Chip Intellectual Property (IP) Cores What they do: These companies design and license specific components or blocks of a chip, such as processors, memory controllers, or communication interfaces. Example: Arm (CPU cores), Imagination Technologies (GPU cores), Cadence Design Systems (IP for various functions) 2. Electronic Design Automation (EDA) Tools What they do: These companies provide software tools used by chip designers to create, simulate, and verify chip designs. Example: Synopsys, Cadence Design Systems, Mentor Graphics (now Siemens EDA) 3. Specialized Materials What they do: These companies supply the specialized chemicals, gases, and other materials used in the chip manufacturing process. Example: Air Products, Linde, Tokyo Electron 4. Wafer Fab Equipment (WFE) What they do: These companies manufacture the complex machines and equipment used in semiconductor fabrication plants (fabs). Example: ASML (lithography machines), Applied Materials, Lam Research 5. "Fabless" Chip Companies What they do: These companies focus on designing chips but outsource the manufacturing process to foundries. Example: Qualcomm, NVIDIA, MediaTek 6. Integrated Device Manufacturers (IDMs) What they do: These companies design, manufacture, and sell their own chips. Example: Intel, Samsung, TSMC (also a foundry) 7. Chip Foundries What they do: These companies specialize in manufacturing chips for other companies, using their own advanced fabrication processes. Example: TSMC, Samsung, GlobalFoundries 8. Outsourced Semiconductor Assembly and Test (OSAT) What they do: These companies provide packaging, testing, and final assembly services for semiconductor chips. Example: ASE Group, Amkor Technology, Kyocera If you are investing in semiconductors and looking for expert insights, drop us a DM. For all semiconductor and AI related insights, follow TechoVedas ------ P.S : If you like writings like these, we have compiled 100s of such questions in our book- The semiconductor Saga- a book that teaches you everything about semiconductors in simple words. Link in comments.

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AXI (Automated X-ray Inspection) is becoming critical for both advanced semiconductor nodes and 2.5D / 3D advanced packaging. Advanced packaging makes “invisible defects” the dominant failure mode. AXI is no longer optional—it’s foundational infrastructure. Why AXI Is Becoming Essential 1. Packaging Complexity Is Exploding Advanced packaging introduces hidden structures that cannot be inspected optically: ➡Micro-bumps (≤ 20 µm, moving toward single-digit µm) ➡Cu-Cu hybrid bonding ➡TSVs (Through-Silicon Vias) ➡RDL layers in Fan-Out / Fan-In ➡Interposers (silicon & organic) ➡ Optical inspection cannot see inside ➡ AXI becomes the only viable non-destructive solution Key AXI Use Cases in 2.5D / 3D Packaging for Micro-bump & Hybrid Bond Inspection Detect: ➡Voids ➡Non-wet opens ➡Misalignment ➡Partial bonding defects Critical for: ➡Chip-on-Wafer (CoW) ➡Wafer-on-Wafer (WoW) ➡Die-to-Die bonding 🔹 TSV Integrity (AXI enables detection of) ➡Voids in TSV fill ➡Seam defects ➡Mis-etch / incomplete fill ➡Cracks after thermal cycling 🔹 RDL & Interposer Inspection (AXI helps verify) ➡Line continuity ➡Shorts / opens ➡Mis-registration between layers ➡Hidden delamination Advanced substrate inspection ➡ Yield loss at advanced nodes is extremely expensive, so early AXI detection = major cost savings Technology Trends in AXI ➡Higher Resolution & Energy Control ➡Sub-micron focal spot X-ray sources ➡Variable energy for different materials (Cu, Sn, Si) AI-Driven Defect Classification ➡Automated void quantification ➡Pattern recognition for bonding anomalies ➡Reducing false calls in high-volume manufacturing Resolution vs. throughput is the fundamental bottleneck of AXI, and it’s becoming more painful as 2.5D/3D packaging scales. ➡The Core Trade-off: Resolution ↔ Throughput To resolve micro-bumps, Cu-Cu bonds, TSV seams, AXI needs: ➡Smaller X-ray focal spot ➡Higher magnification ➡Longer exposure time ➡More projections (for CT / laminography) You cannot simultaneously maximize: ➡Resolution ➡Throughput ➡Field of view ➡Penetration depth Hybrid Inspection Strategy  (Most Common) ➡Inline low-res AXI → screen gross defects ➡Offline high-res AXI / CT → root cause & qualification

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This chart show the manufacturing processes to produce various types of purified silicon for solar, semiconductor and battery anode applications. However, it is incomplete because if only shows CVD nano-silicon in engineering Carbon (second arrow in the lower portion of the graph). See my just prior post for the detailed explanation of the SINANODE process to produce, using CVD, the nano-silicon inside the pores of EV-grade graphite particles rather than inside highly engineered and expensive porous hard carbon substrates. The SINANODE process is far more efficient and far less expensive for at least three reasons: (1) The substrate to host the silicon is already produced in large quantities and high quality by suppliers already qualified with EV cell factories. This saves time and money. (2) The silane is decomposed into silicon using a catalystic process rather than a thermal decomposition process. This saves time (by a factor of at least 5), energy (lower decomposition temperature), and waste (near 99% of the silane is decomposed into silicon and the hydrogen is recovered to make more silane; whereas thermal decomposition is slow and partial, typically less than 70% conversion into silicon). (3) Because the SINANODE composite comprises graphite particles enhanced with nano-silicon, the slurry preparation, electrode coating, electrode calendaring and cell formations processed are standard to all EV cell factories. Other technologies, including HC-Si composite, require mixing of new composite particles, new slurry formulations, new coating specifications, and the electrodes cannot be calendared to the nornal values (i.e. 1.6 to 1.7 g/cc). Often, the anode layers comprising HC-Si are too thin to be uniformly coated at high speed (> 100 m per min) on large EV cell electrode coating machines. Finally, safety of SINANODE materials is derived from using EV-grade graphite with known thermal and chemical properties for years. By contrast, the very large internal surfaces inside microporous hard carbon substrate present high safety risks when a thermal runaway condition leads to electrolyte leaking inside the HC-Si particles and in contact with very large amount of silicon surface, i.e. many many tens of sq. meters per gr). #EVbatteries #silicon #anodes

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TSMC Exits GaN Foundry Business — Is IDM the Winning Formula for Gallium Nitride? TSMC has confirmed its complete exit from the GaN wafer foundry market by 2027, signaling a turning point for how the industry approaches gallium nitride production. While traditional foundries step back, players like Infineon and China’s Innoscience are charging ahead, backed by an IDM model and deep vertical integration. 🔘 Why is the foundry model losing traction in GaN? According to Innoscience Chair Weiwei Luo, power GaN devices aren’t well-suited for the traditional foundry model. These devices require close coupling between design, epitaxy, process, and application, which the foundry-client model struggles to support. Instead, IDM offers the agility and control needed to meet market demands. 🔘 Process Clues: GaN Is Fundamentally Different GaN devices may involve ~100–150 process steps, primarily around MOCVD epitaxy, isolation, and device fabrication on 8-inch wafers. By contrast: - Silicon superjunction MOSFETs require ~200–250 steps with complex trench and doping processes at ~0.18–0.35 µm nodes. - Advanced logic CMOS runs beyond 1,000 steps at 5–28 nm nodes. GaN’s value lies in material advantages not lithographic scaling. This makes it better suited for power efficiency at higher voltages and frequencies, rather than density or integration. 🔘 IDM Momentum Is Building Innoscience is already delivering: - 13,000 wafers/month by end-2024, aiming for 70,000 wafers/month by 2028. - Full-spectrum 8-inch GaN-on-Si product lines. - AI/datacenter GaN shipments up 669.8%, EV-grade up 986.7% YoY. - Mass production of 100W GaN drivers for humanoid robotics. Though 12-inch GaN is on the roadmap, MOCVD tools aren’t yet ready for production-grade 12” GaN epitaxy, making 8-inch the current industry sweet spot. 🔘 What’s Next for the GaN Market? - Global GaN power device market projected to reach $4.38B by 2030 (TrendForce). - Growth driven by EVs, AI data centers, robotics, and industrial power. - IDM players with process control and vertical integration will likely lead. Foundry models optimize for volume and versatility. GaN, by contrast, demands vertical specialization and tight design-manufacturing coupling. 💡 TSMC’s exit may mark a turning point for differentiated manufacturing strategies—one that favors depth over breadth, collaboration over commoditization, and value-chain ownership over transactional scalability. Reference sources: https://lnkd.in/g5DzSKap ; https://lnkd.in/gXXrdsn8 Let’s shape the future together: 👉 https://lnkd.in/gJ3SSg8c #GaN #PowerElectronics #TSMC #IDM #Innoscience #Semiconductors #Infineon #EV #MOCVD #TechStrategy #12InchWafer #AdvancedPackaging

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When I started ATLANT 3D in 2018, investors often asked: “Who actually needs atomic-scale manufacturing outside semiconductors?” Fair question. At the time, chip fabs had tightly integrated ALD systems. Universities had limited access. Everyone else waited. Atomic-scale manufacturing looked niche. Today, it’s a very different conversation. - Battery teams working on solid-state cells need atomic-scale control of interfaces. - Quantum hardware teams need reproducible material stacks with minimal variability. - Photonics companies need precision structures where nanometers matter. - Space and defense programs need localized, on-demand manufacturing. - Materials labs need to iterate as fast as AI can propose new compounds. So what changed? Three things converged. → 1st: Materials design accelerated dramatically. AI and simulation can now explore vast design spaces. Fabrication became the bottleneck. → 2nd: Supply-chain shocks exposed the fragility of centralized manufacturing. Governments and industry started taking distributed production seriously. → 3rd: New technologies reached a point where performance is dictated by interfaces, not just architecture. Atomic-scale control moved from “nice to have” to “make or break.” Nothing about our vision changed. What changed is that atomic-scale manufacturing is no longer a specialized toolchain for fabs. It’s becoming foundational infrastructure for multiple industries. In deep tech, timing matters. Sometimes you’re too early. Sometimes you’re too late. And sometimes you’re building exactly what the world needs before it has the language to ask for it. That’s where atomic-scale manufacturing is today. The question is no longer who needs this. It’s how quickly we can make it accessible at scale.

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Today, OpenAI and Cerebras announced they have signed a multi-year agreement to deploy 750 megawatts of Cerebras wafer-scale systems to serve OpenAI customers. This deployment will roll out in multiple stages beginning in 2026, making it the largest high-speed AI inference deployment in the world. Cerebras delivers the world’s fastest inference service, about 15X faster than Nvidia GPU. This speed is essential for reasoning models and agentic AI to be successful. The world has now recognized what we saw as the critical element in enabling the next inflection point in AI adoption: speed. Cerebras #speed #fastinference

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New York Approves Key Infrastructure for Micron Technology’s $100B Semiconductor Megafab The New York State Public Service Commission has approved a new underground transmission line to connect an existing Clay substation with Micron Technology’s proposed semiconductor megafab in Onondaga County — a critical step in advancing the company’s $100 billion investment, the largest private project in New York’s history. The two-mile, 345-kilovolt line will supply essential power to Micron’s future facility, projected to create over 50,000 jobs across two decades, including 9,000 direct hires. Governor Kathy Hochul emphasized that the project is “set to transform Central New York,” reflecting the state’s rapid progress in semiconductor manufacturing development. The approval also includes environmental and construction plans for the Clay substation’s expansion — marking another milestone since Micron’s 2022 agreement with New York to establish the site. By 2030, the megafab aims to produce 25% of all U.S.-made semiconductors, reinforcing America’s domestic chip supply chain. As infrastructure and policy align, New York continues to position itself at the forefront of U.S. semiconductor revitalization. Thanks to Reuters for providing the full article with additional background, charts, and insights at the link below. 👇 https://lnkd.in/gYEW39wa #ChipDesign,#SemiconductorManufacturing, #VLSI, #Lithography, #ICPackaging

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"Since TSMC's and Rapidus's 2nm-class production nodes are different and the two companies even have different views on how wafers should be processed, it is unlikely that the foundry could get a lot of useful information for its fab from TSMC's 'process integration technical photos.'" There's always international intrigue in the world of semiconductors. https://lnkd.in/eJfypP7R

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Is There a Place for SiC in Sub-200 W AC-DC / PFC Designs Dominated by SJ MOSFETs? In sub-200 W AC-DC and PFC applications, 650 V silicon superjunction (SJ) MOSFETs have long been the default choice. This is not because silicon still holds a material advantage, but because cost structures and established design ecosystems have historically locked out alternatives. If we assume cost parity between 700 V SiC MOSFETs and 650 V Si SJ devices, the basis for device selection changes. When Cost Is Fixed, Design Decisions Return to Device Behavior With cost removed as a differentiator, engineers naturally focus on system-level behavior: Temperature dependence of conduction losses Switching and recovery behavior under real operating conditions Long-term stability and consistency These factors define how much margin a design truly has beyond the datasheet. 650 V SJ Operates Near the Silicon Limit At breakdown voltages approaching 600–700 V, SJ MOSFETs already operate close to the practical limits of silicon. Further optimization relies on structural complexity rather than material margin, leading to strong temperature sensitivity and increased reliance on system-level compensation. This has largely been accepted because no alternative existed in the same cost range. Why the Transition Point Is 700 V SiC This is not about replacing 650 V SJ with 650 V SiC. The meaningful transition occurs when 700 V SiC replaces 650 V SJ. At 700 V, SiC remains well within its material comfort zone, retaining intrinsic margin in temperature behavior, switching dynamics, and long-term stress handling. This does not require a topology change or higher power—only a shift in where the device operates on the material curve. Redefining the Baseline Once cost parity is assumed, continuing to rely on silicon is no longer the default safe choice—it becomes a decision that requires justification. The question is no longer: Why use SiC below 200 W? It becomes: Why continue designing around silicon devices operating at their physical limit? Closing This is not about introducing SiC into low-power applications. It is about removing the need to design around silicon limits when a more tolerant material is available at the same cost level. I do have a 700 V SiC solution designed specifically for sub-200 W applications. If you’re interested in discussing this approach, feel free to contact me. #PowerElectronics #SiC #ACDCDesign #PFCDesign #HighVoltageMOSFET #SiliconLimits #SystemLevelDesign

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*** New To Chiplets World: What I’d Focus On *** As a new engineer entering the world of chiplets, the learning curve is steep, but there are three areas I’d focus on first: 1.Understanding the interconnects. The core of chiplet-based SoCs is the inter-chiplet communication.Whether it’s UCIe, BoW, EMIB, or any other protocol, understanding how data moves between chips is crucial. If you don’t get how chiplets communicate, you won’t understand how your design will work in a multi-die system. 2.System-level thinking. Chiplet designs aren’t about optimizing individual chips—they’re about creating a coherent system. As a new engineer, it’s essential to look beyond the chiplet’s boundary and think about how your piece fits into the larger architecture. Understanding power, thermal, & communication interactions is key. 3.Verification from the start. The hardest issues with chiplets often surface at integration. Focus on building verification strategies early—both at the individual chipletlevel and in the full-chip system. A deep understanding of how chiplets interact will be your biggest asset. If you were starting fresh in the chiplet world, what would you prioritize?

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