Sierra Pak

🚀 Socionext Breaks New Ground with 3DIC & 5.5D Packaging Socionext has officially taped out a next-gen SoC using TSMC’s SoIC-X 3D stacking—combining N3 compute and N5 I/O dies in a face-to-face (F2F) configuration. This milestone slashes latency, boosts bandwidth, and cuts power consumption, redefining what's possible in consumer, AI, and HPC applications. With support for chiplets, 2.5D, 3D, and now 5.5D packaging, Socionext is leading the charge in heterogeneous integration—bringing together multiple tech nodes and functions in a single, high-density package. 🔧 Vertical stacking. ⚡ Lower power. 📦 Smaller footprint. 💡 Limitless potential. #Semiconductors #3DIC #SoC #Innovation #Socionext #TSMC #AI #HPC #ChipDesign #TechLeadership #Hiring #Semiconductorhiring #ASIC #Marketing #TPM #Technicalprogrammanager(s) #SFBAYAREAJobs

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Alphabet's Waymo unit has received approval to expand its autonomous ride-hailing service to more parts of the San Francisco Bay Area, including San Jose. In March, the company submitted a request to the California Public Utilities Commission to gain approval for its latest passenger safety plan, a key step in gaining permission to operate driverless vehicles across a broader area. On Monday, the proposed expansion was approved, allowing for Waymo's driverless coverage to extend from San Francisco down through the Peninsula. "We're very excited to share that the CPUC has approved our application to operate our fully autonomous commercial ride-hailing service in the South Bay and nearly all of San Jose!" the company wrote in a post on X on Monday. "While this won't change our operations in the near-term, we're looking forward to bringing the benefits of Waymo One to more of the Bay Area in the future." This self-driving car technology stock could pop by more than 400%, say thre

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I have been hearing from multiple hiring managers at semiconductor companies that what they look for in senior engineers is starting to change: The "most wanted" engineers today don’t fit perfectly into “hardware” or “software.” They are "hybrids". People who understand chip design and materials, but also know how software, AI models, and data interact with that hardware. Some will say, “that’s nothing new, hardware and software have always worked together.” Of course that is true, but the two areas are much more linked now I am starting to see. It’s not just about firmware anymore. So are chip designers starting to use AI tools to help design chips automatically. For example, using machine learning to optimise chip layouts or reduce power consumption. Big EDA vendors (Synopsys, Cadence) are adding AI capabilities to their tools. They use machine learning to speed up or improve tasks like verification, layout, power/performance/area tradeoffs, and error checking. DeepMind has developed a reinforcement-learning based system that generates chip layouts. The system can design layouts in hours that would normally take weeks. Their layouts have been used (or claimed to be used) in Google’s TPU chips. An other example: System engineers are designing hardware architectures (how the chip is structured) based on how AI models perform. This basically means the hardware is being built to match what AI models need. The integration is now at the core of how products are built. You can see this across the industry: * Nvidia blends hardware and AI expertise in the same teams. * ASML hires engineers who combine optics with data analytics. * Smaller design houses want verification engineers who can script and use AI tools. McKinsey projects the semiconductor industry will need over a million additional skilled workers by 2030, many in roles that blend hardware and software. But many companies still hire as if these disciplines were separate. From my conversations with industry experts, it’s clear that the next generation of AI-enabled chips will depend on teams who understand both sides. With that in mind, if you’re hiring, it might be time to rethink what makes someone qualified. I always suggest to look for curiosity, adaptability, and engineers who’ve worked across layers. Even if their background isn’t a perfect match. From my point of view, these hybrid engineers will make future products possible.

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If you built a distributed, automated, API-first network of micro-factories that can deliver “the China” experience to hardware developers, you’d be enabling the next Compaqs (OG PC revolution), not just being one of them.

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#Altera, Spun Off From #Intel Earlier This Year, Reportedly Cutting Nearly 100 #Jobs According to San Francisco Chronicle, #Altera—the programmable #chipmaker recently spun off from #Intel—plans to cut about 82 jobs at its San Jose headquarters, based on a Worker Adjustment and Retraining Notification (#WARN) filed with the state of California. The job cuts at #Altera were announced last week and are set to take effect in October, according to state filings, as reported by #KRON4. As PeopleMatters notes, citing sources, the layoffs come as part of the company’s transition under new ownership. However, Tom’s Hardware notes that the timing of these changes at Altera coincides with a period of significant turbulence for Intel, which has laid off tens of thousands of employees in recent quarters. As the San Francisco Chronicle highlights, Altera’s layoffs come on the heels of hundreds of recent job cuts by Intel across the Bay Area and the rest of California. #Intel is cutting about 24,000 jobs this year—reducing its workforce by roughly one-quarter, according to a report from The Verge last month. Earlier this year, #Altera was spun off as an independent company. As #PeopleMatters notes, Intel retains a 49% stake after selling a 51% majority share to private equity firm Silver Lake in a deal valued at USD 8.75 billion, which is expected to close later this year. When Intel acquired Altera in 2015 for USD 16.7 billion—its largest takeover at the time—it saw the FPGA maker as a key opportunity to diversify its revenue streams and bolster its position in the data center market, as Tom’s Hardware states. However, the tech giant has struggled to grow Altera’s business. In addition to Altera, as noted by a Tom’s Hardware report from July, Intel is also spinning off its Network and Edge Group (NEX) into a standalone business. Full Article - https://lnkd.in/gv9igs88

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One of my closest school friends now leads several engineering teams in a fast growing series F startup in the Bay Area. He’s based in New York and has to travel to the Bay Area often. (Important later on) A graduate engineer joined his extended team in the Bay Area as his skip report. She’s talented and has scaled up quickly so far. As her first big thing, she was working on a particular feature X (omitting the actual info). In the larger scheme of things though, this feature is a tiny update to the end customer. It’s useful but not something they will remember. During his recent visit to their Bay Area office, my friend met this new joiner at their cafeteria. After a few pleasantries, she mustered up the courage to ask him “In the recent customer calls, did you discuss about my feature?” My friend took a split second and said “yes, we did. They loved it & it’s made their lives easier.” She walked away grinning and happy. And she’s been asking for more work recently. This is not a productivity hack or a trick to get somebody to work more. This is realizing that most human beings crave meaning. My friend told me later “We didn’t discuss the feature explicitly in the calls but it’s definitely made their lives easier.” He helped the new engineer feel important with a single answer in a 1 min interaction. She felt like her work mattered. Human beings are a hot mess. But sometimes, they are also incredibly simple. Help people find meaning in their work and watch the magic unfold. #manager

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Lucid announced a landmark initiative with NVIDIA to accelerate the path to autonomous features for Lucid vehicles. Working together, our team will bring eyes-on, point-to-point driving (L2++) to Lucid Gravity later next year, and one of the first true eyes-off, hands-off, and mind-off (L4) consumer owned autonomous vehicle to future midsize vehicles leveraging NVIDIA’s multi-sensor suite architecture, including cameras, radar, and lidar. Read more about today’s announcement: https://ow.ly/vkfq30sQRi3

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Metamates, here’s how to completely screw up today’s RSU vest: (I’ve done 4 of these) 1. Not calculating that your marginal tax rate is above the default 22% ↳ Bay Area FAANG salaries usually put you in 32%+ territory, not the RSU default 2. Don’t check your withholding rate ↳ It’s probably still set to that 22% while you actually owe 32%+ 3. Think holding = tax benefits ↳ Your RSUs are taxed as ordinary income whether you sell or hold 4. Hold for a year expecting long-term gains treatment ↳ Only the GAIN above vest price gets preferential treatment 5. Have zero plan for selling or deploying the money ↳ I’ve seen folks accumulate multiple 6-figure concentrated positions because they didn’t have a plan and didn’t take action What’s your biggest RSU lesson learned the hard way?

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🚀 Static Timing Analysis (STA) Engineer: The Unsung Heroes of Silicon Success! 🚀 STA engineers play a crucial role in ensuring that complex ASICs and SoCs meet stringent timing requirements across all process, voltage, and temperature corners. 🔍 What makes an STA Engineer critical? Expertise in timing constraint creation and management (SDC) Mastery of STA tools like Synopsys PrimeTime, Cadence Tempus, and TimeVision Deep understanding of setup/hold violations, clock domain crossings (CDC), multi-corner multi-mode (MCMM) timing closure Ability to analyze timing reports and collaborate with RTL, synthesis, and physical design teams to fix timing issues Strong scripting skills in Tcl, Perl, Python for automation and timing data parsing 🎯 Industry Demand & Challenges: Experienced STA profiles are quite rare, making them highly sought-after in semiconductor companies. Many effective paths include transitioning from RTL design verification or physical design backgrounds with focused STA training. STA engineers are key contributors to silicon signoff, power-aware timing closure, functional safety timing checks, and ensuring product reliability. 💡 Career Tips for Aspiring STA Engineers: Build a solid foundation in RTL and digital design fundamentals. Gain hands-on experience with STA tools and constraint scripting. Understand cross-domain timing challenges and low-power design impacts. Continuously collaborate with multi-disciplinary teams (synthesis, PD, verification). I If you’re an STA professional or looking to break into STA, share your journey or tips below! For recruiters seeking STA talent, investing in training can pay off massively by enabling strong internal STA capabilities. #StaticTimingAnalysis #STAEngineer #ASICDesign #PrimeTime #CadenceTempus #TimingClosure #TclScripting #SemiconductorJobs #VLSI #EDAtools #TimingVerification #RTLDesign #PhysicalDesign

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Keeping the balance between practical applications and excitement...Aaron Prather says it well in the video below. On the topic of robotics, we recently released a bonus episode on "The State of Robotics" in advance of the upcoming RoboBusiness event in Santa Clara. Still, many of the topics that came up with experts like Aaron and Spencer Krause at this year's Robotics Summit are still going to be in the discussion. Catch our full set of interviews hosted by Chris Luecke and Jake Hall in this compilation episode: https://lnkd.in/gw7dBC3E Stay Innovative, Stay Thirsty #robobusiness2025

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When it comes to autonomous driving, Tesla and Waymo couldn’t be more different in how they approach the problem, and what they believe it will take to solve it. Waymo is all-in on the “hardware-heavy” school of thought: LiDAR, radar, HD maps, redundant compute, and highly curated geo-fenced environments. It’s a masterpiece of engineering, no doubt. And it works, but only in specific cities, under tightly controlled conditions, and with a very high operational cost. Tesla, on the other hand, is betting on vision and scale. No LiDAR. No HD maps. Just neural networks trained on billions of real-world miles, constantly updated from a global fleet of cars. Less hardware. Lower cost. More scale. And most importantly, a direct path to consumer vehicles, not just robotaxi pilots. From a tech perspective, the contrast is clear: • Waymo builds autonomy like it’s building a #NASA mission. • Tesla builds it like it’s scaling a #smartphone feature. I’m leaning toward Tesla’s approach, not because it’s perfect, but because it’s data-rich, less dependent on expensive hardware, and more #economically viable in the long run. Of course, the race isn’t over. #Regulations, edge cases, and safety validation will shape the outcome. But if autonomy is ultimately a software problem at scale, I think Tesla may be closer than we think. HITEC Angeles Investors The Tech Series Porsche AG Pirelli NASA - National Aeronautics and Space Administration General Motors Rivian BYD U.S. Department of Transportation OpenAI

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💀 Forcing Great Engineers into Management is Corporate Suicide. There is a false, destructive career ladder in tech: To advance your salary and influence, you must become a people manager. This is a catastrophic mistake, especially in highly specialized fields like firmware and embedded systems. We take our most brilliant technical minds, the ones who truly understand: Clock domain crossing. How to read a datasheet and predict hardware behavior. Debugging a system with zero visibility. ...and we exile them to a world of performance reviews, budget meetings, and HR paperwork. The outcome is a complete mismatch of skills: We lose a great engineer, gain a mediocre (and often miserable) manager, and starve the team of the necessary deep technical guidance. The Solution: A Genuine Dual-Track Career Ladder The only way forward is to create a career path where individual technical contribution is valued as highly as people management. A Principal Engineer or Technical Fellow must have compensation, influence, and respect equivalent to a Director or VP. Their job is not to manage people, but to: Manage Complexity: Set the overall technical architecture. Ensure Quality: Act as the ultimate gatekeeper for elegant, simple, and reliable designs (choosing what not to build). Provide Mentorship: Be the ultimate technical coach for the entire organization. Stop penalizing your technical experts by forcing them to abandon their craft. Elevate the technical path. 🔥 Engineers & Leaders: Have you seen a great technical mind fail in management? Or, more positively, have you seen a company that actually gets the dual-track system right? What did that successful technical track look like? #Firmware #EmbeddedSystems #EngineeringManagement #TechnicalLeadership #CareerDevelopment #DualTrack #TechnicalFellow

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Our CEO Jensen Huang joined Y.L. Wang, TSMC vice president of operations, and Ray Chuang, CEO of TSMC Arizona, in Phoenix today to celebrate the first NVIDIA Blackwell wafer produced in the United States. This achievement marks a huge step forward in paving the way for sustained American leadership in AI. Onshoring world-class chipmaking to American soil is crucial to meeting the growing demand for AI. Within the next four years, NVIDIA plans to produce up to one-half-trillion dollars of AI infrastructure in the U.S. — collaborating with TSMC, Foxconn, Wistron, Amkor Technology, Inc., and SPIL 矽品. Manufacturing the world’s AI technology stack in America will fuel innovation and bolster the US supply chain. The production of American AI factories is projected to create hundreds of thousands of jobs and drive trillions of dollars in economic security over the coming decades. Read more: https://bit.ly/470eLM6

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Our CEO Jensen Huang joined Y.L. Wang, TSMC vice president of operations, and Ray Chuang, CEO of TSMC Arizona, in Phoenix today to celebrate the first NVIDIA #Blackwell wafer produced in the United States. This achievement marks a huge step forward in paving the way for sustained American leadership in #AI. Onshoring world-class chipmaking to American soil is crucial to meeting the growing demand for AI. Within the next four years, #NVIDIA plans to produce up to one-half-trillion dollars of AI infrastructure in the U.S. — collaborating with TSMC, Foxconn, Wistron, Amkor Technology, Inc., and SPIL 矽品. Manufacturing the world’s AI technology stack in America will fuel innovation and bolster the US supply chain. The production of American AI factories is projected to create hundreds of thousands of jobs and drive trillions of dollars in economic security over the coming decades. Read more: https://bit.ly/4obXUMn #AIFactory #DataCenter

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What does acceleration feel like to an engineer? On the left: hours lost to data prep and workflow restarts. On the right: that time reclaimed for modeling, testing, and shipping. Faster hardware doesn’t just cut tasks, it changes the shape of your day. Chapter 4 of The Codex report walks through the math and the culture shift that follows. 🔗https://lnkd.in/gGXhxe78 #theseus #VoltronData

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