Milpitas, California, United States
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I am a highly motivated and creative firmware architect with 19 years of experience in…

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Experience & Education

  • Broadcom

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Licenses & Certifications

Volunteer Experience

  • Member

    Aid India, Buffalo

    - 1 year 7 months

    Education

    Participating in meeting to decide goals and projects to fund, raising awareness

  • Freedom English Academy, FEA Graphic

    Mentor

    Freedom English Academy, FEA

    - Present 8 years 1 month

    Education

    Mentoring youths and providing career guidance

Publications

Patents

  • Creating isolation between multiple domains in a hierarchical multi-tenant storage device

    Issued US12236138B2

    See patent

  • Maintaining predictable latency among tenants

    Issued US20240329864A1

    See patent

  • Solid state drives with improved format handling

    Issued US20240094928A1

    See patent

  • Enhanced trim command support for solid state drives

    Filed US US20200081830A1

    In an SSD including a host interface, controller, non-volatile memory coupled to the controller, and volatile memory, data is stored in non-volatile memory in clusters having a cluster start address and a cluster end address. A mapping table is maintained in volatile memory, which indicates by a trim signature deallocated clusters in non-volatile memory. The trim table is populated with deallocated ranges and an associated offset within the non-volatile memory. The controller receives from the…

    In an SSD including a host interface, controller, non-volatile memory coupled to the controller, and volatile memory, data is stored in non-volatile memory in clusters having a cluster start address and a cluster end address. A mapping table is maintained in volatile memory, which indicates by a trim signature deallocated clusters in non-volatile memory. The trim table is populated with deallocated ranges and an associated offset within the non-volatile memory. The controller receives from the host interface a sequence of commands including a deallocate command including at least one address range including a start address and an end address, or a start address and a length of the address range. The controller processes the deallocate command by selecting one or both of a write-to-non-volatile-memory action and a record-to-volatile-memory action. In cases of power failure, the mapping table is restored for deallocated ranges at specific offsets recorded in the trim table.

    Other inventors
    See patent

  • Configurable Data Placement with Variable Plane Programming to support multi-stream SSD

    Filed U.S. Application Number: 18/963,29

    Configurable data placement with variable plane programming model to support multi-stream SSD with limited volatile write cache buffer

    The invention proposes a new firmware design of configurable data placement in the Nand wordlines and variable plane cache programming as per the write traffic of individual streams.
    The new design also introduces the term of minimum write cache control buffer (mWCCB) to quickly release and reuse the buffers during the data transfer to the Nand at a…

    Configurable data placement with variable plane programming model to support multi-stream SSD with limited volatile write cache buffer

    The invention proposes a new firmware design of configurable data placement in the Nand wordlines and variable plane cache programming as per the write traffic of individual streams.
    The new design also introduces the term of minimum write cache control buffer (mWCCB) to quickly release and reuse the buffers during the data transfer to the Nand at a much smaller granularity during Nand programming .
    This novel approach of shortening the life-time of write buffers helps in managing variable write workload with limited volatile write cache buffer without compromising on write performance.
    In other embodiments with high OP (over provisioning), to reduce latency requirement of low QD (queue depth) large read commands after a slow write traffic, the invention proposes an alternative method to use SLC blocks to aggregate partial data needed to fill a wordline for slow moving traffic, before eventual programming to the corresponding user data block of the stream.

    Other inventors

  • Conservation of over provisioning in Nand based SSD through improved programming scheme to handle bad blocks.

    Filed US Application No. 63/703,348

    The invention proposes a new method of processing a multi-plane program operation in a wordline containing one or more (but not all) bad pages i.e. pages belonging one or more bad blocks of the multi-plane block.
    For the pages belonging to the bad blocks, the new design skips the scrambler, CRC generator and LDPC encoder and fills up the buffer with raw data of all ones.
    This novel approach thus skips programming the pages of the bad block in a multi-plane program operation.
    In other…

    The invention proposes a new method of processing a multi-plane program operation in a wordline containing one or more (but not all) bad pages i.e. pages belonging one or more bad blocks of the multi-plane block.
    For the pages belonging to the bad blocks, the new design skips the scrambler, CRC generator and LDPC encoder and fills up the buffer with raw data of all ones.
    This novel approach thus skips programming the pages of the bad block in a multi-plane program operation.
    In other embodiments where it is not possible skip the Scrambler, CRC generator and LDPC encoder for specific pages in a multi-plane wordline, the patent proposes that firmware checks the program status on only the good planes until programming on all the good planes completes and then terminate the multi-plane program operation.
    The patent thus provides an efficient way of multi-plane program on wordlines containing one or more (but not all) bad planes without consuming the Over-provisioning of the drive and without loss in write performance.

    Other inventors

  • Namespace Data Segregation to Enable Efficient Data Handling and Secure Erase in Multi-Namespace SSD

    Filed US Application No. 63/687,629

    The invention proposes a Hardware-firmware codesign to segregate data belonging to different namespace into different wordlines to ensure efficient handling of different namespace data with different LBA formats containing different LBA data and metadata size.
    The invention also proposes maintaining separate VDF count per namespace in each superblock.
    The new design ensures that fast User Data Erase can be performed as part of Secure Erase by programming the wordlines to G-state, if…

    The invention proposes a Hardware-firmware codesign to segregate data belonging to different namespace into different wordlines to ensure efficient handling of different namespace data with different LBA formats containing different LBA data and metadata size.
    The invention also proposes maintaining separate VDF count per namespace in each superblock.
    The new design ensures that fast User Data Erase can be performed as part of Secure Erase by programming the wordlines to G-state, if requested by the Host during a Namespace Format command with low firmware overhead and without reclamation/movement of data belonging to other namespaces, thereby reducing command latency, write amplification and enhancing drive life.
    In case of reclaim superblocks, the new design keeps track of the source superblocks from which data is reclaimed, so that previous location of the data in the free source superblocks can also be corrupted, during a Namespace Format command with user data erase.
    The new design of data corruption through programming to G-state also ensures low latency processing for Sanitize command and Format command with user data erase for Zoned Namespace.

    Other inventors

  • Mitigating data decoding failures using data logs.

    Filed US Application No. 63/675,738

    The invention proposes a firmware design to reduce UBER (uncorrectable bit error rate) of the SSD drive and improve Read latency (QoS) by creating and recording Data Tracking (DT) Logs for reclaimed Virtual Blocks at the end of each Virtual Wordline before the Raid parity pages.
    Data Tracking logs on the GC (Garbage collection) blocks containing cold data will record the prior physical address of each reclaimed data frame in the Virtual wordline and use the prior physical address to read…

    The invention proposes a firmware design to reduce UBER (uncorrectable bit error rate) of the SSD drive and improve Read latency (QoS) by creating and recording Data Tracking (DT) Logs for reclaimed Virtual Blocks at the end of each Virtual Wordline before the Raid parity pages.
    Data Tracking logs on the GC (Garbage collection) blocks containing cold data will record the prior physical address of each reclaimed data frame in the Virtual wordline and use the prior physical address to read the data in case the Read Retry attempts fails to recover the data in the current virtual block.

    Other inventors

  • Validity Table for Solid State Drives

    Filed 20230096420

    Other inventors
    See patent

  • SSD supporting Deallocate Summary bit Table and Associated operation

    Filed 20230095644

    Other inventors
    See patent

  • DYNAMIC BUFFER CACHING OF STORAGE DEVICES

    Filed 17/025,898

    Other inventors
    See patent

Courses

  • Biomedical Intrumentation

    -

  • Computer Architecture

    -

  • Computer Architecture

    -

  • Computer Vision and Image Processing

    -

  • Control Systems

    -

  • Digital Communication

    -

  • Digital Electronics

    -

  • Digital Signal Processing

    -

  • MIMO Wireless Communication

    -

  • Microprocessor Based Instrumentation

    -

  • Optical Instrumentation

    -

  • Probability and Stocastic Processes

    -

  • Telemetry

    -

Languages

  • English

    Full professional proficiency

  • Bengali

    Native or bilingual proficiency

  • Hindi

    Native or bilingual proficiency

  • Assamese

    Native or bilingual proficiency

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