Nilesh Dattani

*** Silent Killer in High-Speed Interface Design *** Every engineer working on PCIe, USB, CSI, DSI, LPDDR, SerDes, or any high-speed interface knows: "Timing closure will keep you Up at night." But here’s the thing—It is not always the big violations that kill a design. These can be found and fixed. The silent killers are the marginal cases: * That one Async Clock Domain Crossing that looked fine… until Silicon. * That Power mode Transition that only happens under rare Conditions. * That Corner case in Equalization that only fails in a specific voltage/temp combo. "These don’t show up in the standard verification flow. You have to hunt them down." What’s your approach to catching these hidden pitfalls?

164

5 Comments

Hiring patterns changed. RAM prices explained. Hiring strategy across semiconductor companies has quietly shifted. 1. Less generic VLSI hiring 2. More demand for HBM & memory architecture experts 3. High-speed interfaces & advanced packaging 4. Bandwidth, power, and performance specialists That was the first signal. Then came my deductions AI doesn’t just need compute — it needs memory bandwidth. So memory companies shifted capacity from commercial DRAM to HBM for data centers and AI accelerators. What followed was inevitable: Less commercial RAM supply Same demand Higher prices everywhere This isn’t inflation. This is AI-driven prioritization. Your laptop RAM is now competing with AI data centers. And AI always wins. Strategic shift by memory vendors Slowing consumer & commercial DRAM Aggressively pushing HBM for AI & data centers Fewer wafers for PCs, phones, laptops More capacity reserved for high-margin HBM stacks Result? Even regular RAM feels expensive. Hiring patterns tell the future before prices do. Watching how the HBM ecosystem evolves across memory, foundry, and AI platforms. SK hynix / Samsung Electronics / Micron Technology / NVIDIA / AMD / Intel Corporation / TSMC / Amkor Technology, Inc. / ASE Global 💬 Curious to hear from memory, SoC, and system architects — Is HBM the biggest silent disruptor of this decade?

38

1 Comment

The future of SoC verification is here... Calibre's 2nd-gen Verilog-to-LVS achieves up to 4X faster translation and 92% less memory use for SoC signoff. Get a look at the architecture powering advanced verification results in this paper available here

36

2 Comments

Secrets of Successful Full Chip XTalk ECOs   Quick recap for PD and STA engineers  XTalk ECOs usually hit when the design is almost frozen and SI on STA suddenly turns a clean chip into a problem. In deep sub micron SoCs, coupling heavy interconnect can flip a small positive margin into a violation once you move from block level to full chip.  Why it hurts at full chip  - Block clean is not equal to chip clean. At top level, timing windows change, new aggressors appear, and marginal paths fail when SI is enabled.   - SI off versus SI on gap. Long buses and macro channels pick up large delta delays and noise glitches that never showed up in non SI runs.   - Time pressure. Full chip SI STA across corners is slow, so random ECOs and trial and error can easily waste days.  How the tool really sees XTalk  SI STA loads coupled SPEF, builds early and late arrival windows, finds overlapping aggressors, and computes two key effects:  - XTalk delay: extra delta delay on victims that can dominate cell delay on long coupled nets.   - XTalk noise: glitches on quiet nets compared against library noise immunity limits.  A net is risky when it is highly coupled and its timing window overlaps with many neighbors.  A practical 5 step flow   1. Baseline SI setup-Coupled parasitics loaded, SI delay and noise enabled on key corners, reports and slack sanity checked. 2. First SI on sweep-Run full chip SI STA, dump timing with delta delay breakdown and noise reports for worst nets and endpoints.   3. Cluster, do not chase one by one-Group violations into patterns like long buses, dense hotspots, macro channel routes, and noise only control or reset nets.   4. Targeted fixes per pattern-Long buses: move to higher metals, add spacing, add shields. Hotspots and channels: tighten routing constraints and relieve congestion. Interfaces: use SI aware ILMs and clean boundary routes. Noise only: strengthen victims, upsize drivers where safe, add guard nets. 5. Incremental iterate-Reextract changed regions, rerun SI on critical corners, then stop when SI on margins and noise limits meet your signoff bar.  ECO tricks that usually work   - Prefer routing fixes like spacing, shielding and layer promotion over blind buffer drops.   - Use buffers to split very long victims and shift timing windows, but always check setup and hold and watch for new aggressors.   - Upsize carefully. Stronger victims see less noise, but stronger aggressors can hurt nearby nets and increase IR and EM stress.   - SI on STA shows no unwaived setup or hold violations on required signoff corners.   - Noise checks show peaks and widths within limits on sensitive nets like resets, enables and clock gating controls.   - No single net contributes large XTalk delta delay to many critical paths without a clear mitigation or waiver.  If you treat XTalk critical, cluster violations, automate, and no random net fixes, FC SI ECOs become tough but predictable instead of a last minute tapeout shock.

50

🚀 #100DaysOfRTL — Day 23 🔹 Topic: BCD to Excess-3 Converter in Verilog Today’s RTL design focuses on converting BCD (Binary Coded Decimal) numbers to Excess-3 (XS-3) code — a classic transformation used in digital systems to simplify BCD arithmetic and display logic. 💡 What is Excess-3 Code? Excess-3 is a non-weighted binary code used to represent decimal digits. It is obtained by adding 3 (0011) to the BCD value of a digit. For example: • BCD 0000 → XS-3 0011 • BCD 0101 → XS-3 1000 🧠 Why Use Excess-3? • Simplifies certain BCD arithmetic operations • Self-complementary (good for 9’s complement subtraction) • Avoids invalid BCD states in arithmetic circuits • Useful in display encoding and legacy digital electronics 🛠 RTL Implementation Styles: • Behavioral: using case logic • Gate-level Boolean logic: Optimized version using only logic gates for hardware-efficient synthesis(without use of adder) ��️ Applications: • Decimal arithmetic units • Microcontroller-based systems 📄 Code & Explanation: Attached in the PDF 📌 Follow my progress on GitHub: https://lnkd.in/gzK3eE-x #RTL #Verilog #DigitalDesign #BCD #Excess3 #FPGA #CombinationalLogic #HardwareDesign #EDA #SystemDesign #VLSI #100DaysOfCode #LearningByBuilding #100DaysOfRTL

34

Is VLSI Talent Acquisition still seen as a cost center in 2025? Let’s change that. Every chip company wants the best ASIC, SoC, and Firmware talent. But not every company treats hiring as a strategic function. Too often, I see: 🔸 Hiring plans driven by urgency—not roadmap alignment 🔸 Recruiters chasing unrealistic timelines without clear JD-to-skill mapping 🔸 Interviewers chosen by availability, not capability 🔸 Offers made before stakeholder calibration is complete But when hiring works—it changes everything: 💥 Execution speed 💥 Team morale 💥 Retention 💥 Tapeout timelines So why are TA leaders still fighting for a seat at the table? If 2025 is the year of GenAI and semiconductor resurgence— It must also be the year TA becomes a business partner, not a backend service. What I believe: ✅ Every headcount should tie back to silicon delivery KPIs ✅ TA should sit with engineering leadership—not behind them ✅ Interviews should be structured like design reviews: consistent, data-backed, and outcome-driven Talent drives silicon. TA should drive strategy. If you're in TA, HR, or leadership in the VLSI space—what’s still holding us back from making this shift? Let’s start the conversation. 💬 #VLSI #Semiconductor #TalentAcquisition #HiringStrategy #Leadership #GenAI #TapeoutSuccess #RecruitingReimagined

11

Stunned by how Cerebrus rewrites the rules of RTL-to-GDS? You're not alone and this post kicks off a 5-part technical series for VLSI engineers making the leap from traditional Innovus flows to the AI-powered Cerebrus environment. 🎯 Part 1: Basic Setup & Run From TCL Scripting to Cerebrus Flow In a classic Innovus flow, VLSI engineers manually drive synthesis, placement, and routing with TCL scripts. Think of commands like: • source read_design.tcl • setPlaceMode -congestionDriven • placeDesign • optDesign -postCTS • routeDesign But with Cadence Cerebrus, you move from line-by-line scripting to a configuration-driven, AI-guided flow. A basic YAML configuration (e.g., cerebrus_config.yaml) replaces the need for manual tool invocations. You simply define your: • Project and design names • RTL source files • Constraints (.sdc) • Optimization goals (power, timing, area) Then, you launch the flow using a single command: cerebrus run -cfg cerebrus_config.yaml ✅ Key Shift: Instead of writing and debugging custom scripts at every step, Cerebrus orchestrates your entire RTL-to-GDSII implementation with high-level optimization goals. It intelligently manages tool settings, runs, and results freeing engineers to focus on architecture and quality. This isn’t just a TCL replacement it’s a mindset shift toward self-optimizing, parallelized, and data-driven digital design. 🔥 Stay tuned for Part 2: Hyperparameter Sweeps Made Easy Next, we’ll explore how Cerebrus automates design exploration using reinforcement learning sweeping tool knobs and optimizing for PPA goals intelligently. #VLSI #EDA #CadenceCerebrus #ChipDesign #RTLtoGDS #PhysicalDesign #Semiconductor #AIinVLSI #DesignAutomation #Innovus #ASIC #DigitalDesign  

56

1 Comment

I'm finding myself more and more using GenAI to speed-up system development, it's getting uncannily good and seamlessly moving from descriptions through C, Python and even SystemVerilog. Over two years ago I posted about testing my standard RTL interview question -- the glitchless clock mux. Clocks and clock-domain crossings are where the chip killers are. Two years ago the tech was failing miserably, how is it doing today? Well, SUCCESS but with a significant caveat! The first attempt was close, but it failed to generate SystemVerilog that uses two different pipes to enable and disable the clocks. The most interesting part, I could tell the tool what it had done wrong in plain English, and I got a working glitchless clock mux in the 2nd attempt. Final thoughts: - GenAI is real, and it can significantly accelerate your work if you embrace it - You had better understand the output work product - You can add your expert thoughts and guide the system - You can't skip the testbenches and testing infrastructure So I still think I have some job security in building chips -- but the gap is getting closer 😀 #genai #synaptics #astra #edgeai

117

10 Comments

the Intel Corporation showcased its #18A process running non-x86 SoCs, from Apple and Qualcomm. I believe this boosts Intel’s foundry push and challenges TSMC’s #N2 in price and performance. Intel recently demonstrated a reference SoC using its 18A process, not based on #x86 architecture. The live demo ran real-world workloads like #3D gaming, #animation, and #4K streaming. This move marks Intel’s intention to evolve from an x86-focused player into a global contract chipmaker. I think this strategy follows internal setbacks, such as #PantherLake's low yields with 18A. To succeed, Intel must show that 18A is not just an internal solution but a flexible node fit for wider industry use. The demo reflects that effort. It used seven #CPU cores across different performance classes and included external #PCIe and controller #IPs. By showcasing compatibility with #ARM and #RISC-V architectures—especially those used by Apple and Qualcomm—Intel is sending a message. I see this as a push to prove that 18A can handle diverse, high-performance workloads beyond Intel’s own chips. This also strengthens Intel’s positioning against TSMC’s N2 node. If 18A matures, I believe it can offer better cost and performance over time. This could make Intel a serious player in foundry services. 📘 MY NEW BOOK RELEASED! 🌍 the Global Chip War   the Global Chip War, uncovers the fierce battle between countries and global companies to control chip technology. This book explains why these tiny chips matter to your life, economy, and future—making it a must-read for anyone who wants to understand tomorrow’s world. 🛒 Grab your copy now on Amazon Kindle!👉 https://lnkd.in/gQxiT7qZ For a deeper understanding of the latest semiconductor technologies, read my book, Semiconductor For All 👉 https://lnkd.in/gzVV2fJm , To explore how chips shape our world and industries, subscribe my YouTube channel, https://lnkd.in/gdksSJG2 #semiconductor #ai #chips #manufacturing #semiconductorforall

246

4 Comments

Equalization in PCIe receivers is a set of techniques used to compensate for signal distortion (mainly inter-symbol interference, ISI) that occurs when high-speed signals travel across lossy PCB traces, connectors, and cables. At PCIe Gen3 and beyond (8 GT/s, 16 GT/s, 32 GT/s), the channel is no longer “transparent,” so the receiver must actively equalize the incoming waveform to recover clean data. ⸻ Equalization Techniques in PCIe Receiver There are three major types of equalization blocks used: 1. Continuous-Time Linear Equalizer (CTLE) • Analog filter placed in the front-end of the receiver. • Provides high-frequency boost and low-frequency attenuation to counteract channel losses (which attenuate high frequencies more). • It is a linear equalizer, so it amplifies both signal and noise at high frequency. • Adjustable CTLE settings allow adaptation depending on the channel characteristics. 2. Decision Feedback Equalizer (DFE) • Nonlinear equalizer applied after the slicer (comparator). • Works by using previously detected bits to cancel ISI in the current bit. • Very effective for channels with long tail ISI. • Advantage: does not amplify noise (unlike CTLE). • Limitation: can suffer from error propagation if a wrong decision feeds back. 3. Feed-Forward Equalizer (FFE) in TX (but coordinated with RX) • Strictly speaking, this is transmitter-side, but part of the PCIe equalization training process. • The transmitter shapes its output waveform using pre-cursor and post-cursor taps (3-tap FFE in PCIe Gen3/Gen4). • The RX participates in equalization negotiation (training sequence TS1/TS2) to request different TX FFE settings. ⸻ Equalization Process in PCIe Receiver • During link training (LTSSM, Link Training and Status State Machine), the receiver evaluates the eye opening and BER using training sequences. • It sends feedback to the transmitter (via protocol-defined messages) requesting adjustments of TX FFE taps. • At the same time, the RX adjusts its own CTLE and DFE settings to maximize eye opening. • This adaptive equalization loop ensures reliable data recovery. ⸻ Summary • CTLE → Analog, boosts high frequency to counter channel loss. • DFE → Digital, cancels post-cursor ISI using past decisions. • TX FFE → Pre/post-cursor shaping, negotiated with RX. • PCIe uses a co-optimized TX+RX equalization scheme to achieve high-speed signaling across lossy board channels.

64

1 Comment

Life of an RTL Designer: More Than Just Writing Code: Who understands? In the semiconductor world, RTL design often looks simple from the outside: write Verilog/VHDL, run simulation, and hand it off. But anyone who has lived this role knows it is far more multidimensional. RTL development is a cycle of deep technical work, constant refinement, and continuous alignment with system requirements. Every project brings a different flavor of challenges: 1. Multiple Modes of RTL Coding From architectural definition to micro-architecture development, RTL coding spans: • Clean, synthesizable Verilog/VHDL for production • Test and debug-oriented RTL to isolate specific corner cases • Timing-aware, constraint-driven RTL to close paths cleanly • Low-power RTL applying clock-gating and power-gating strategies • Parameterized, reusable RTL for scalable designs 2. Verification: The Unseen Half of the Work RTL is only the beginning. The bulk of the engineering effort is ensuring the design behaves exactly as intended: • Simulation-based verification • Assertions, formal checks, linting, CDC/RDC analysis • Functional coverage analysis and coverage closure 3. Board-Level Bring-Up and Testing Even after simulation, the real world has its own constraints: • FPGA bring-up • Debugging signals with logic analyzers and ILA • Timing anomalies that never showed up in simulation • Hardware interactions that demand practical fixes 4. Quality and Compliance Requirements Meeting quality standards is not optional. • Coding guidelines and design reviews • Static analysis and timing sign-off, Power, area, performance trade-offs • AXI/ISO/DO-254/ASIL/Telecom/Avionics compliance 5. Deadlines, Requirements, and Constant Coordination The role requires tight collaboration with architects, verification teams, physical design, and firmware. Requirements evolve, timelines shift, and priorities get redefined. 6. The Reward 😎 When that block passes verification, closes timing, meets power budgets, and integrates smoothly into a larger SoC or FPGA system that is the pride of an RTL designer. You know your logic will run in millions of devices, silently and reliably. This is the life of an RTL designer: A balance of precision, creativity, discipline, and continuous problem solving. Not glamorous from the outside, but deeply fulfilling for those who build the digital logic behind tomorrow’s products. Agreed ? Cheers!  Happy Weekend ! #RTL #FPGA #Silicon #Project #Verilog #VHDL #AMD #Xilinx #Life #Engineer #Design #Standard #Quality #CDC #Challenge #platform #Vivado #simulation #Verification #Timing #Closure #Algorithm #AXI #ISO #ASIL #Telecom #Avionics #Aerospace #Defense #Medical #HLS #versal #Kria #Artix #UltraScale #Creativity #Discipline #Glamorous #Architect #Physical #firmware #problem #Solution #logic #ILA #hardware #software #Behavioral #Functional #Test #Debug #Power #budget #Area #Performance

71

1 Comment

🛠️ Tools don’t make you an ASIC designer. I’ve spoken to dozens of engineers. Some seeking mentorship, some at interviews and at the corporate gatherings. Almost all of them believe they can’t grow in ASIC because they lack tool access. But here’s the truth: Tools are not the bottleneck. Understanding is. It’s not wrong to explore tools. In fact, you should. Tools help connect theory to practice. But chasing tools without understanding why flows exist, or how constraints shape a design — that’s where many fall short. Most interviews won’t ask which tool you used. They’ll ask: – Why would a design fail timing even after fixing the logic? – What makes resets so tricky across IPs? – Why can two engineers using the same tool get opposite results? The answer isn’t in the tool. It’s in the methodology. Methodology is how real design happens. It binds together: • ✍🏽 The design • 🎯 The constraints • ⚙️ The configuration Fun Fact: The ASIC tool are way more scalable and free that, running them without methodologies is like designing something aimlessly. Each company adapts it for every IP or SoC. And if you understand methodology, you can work with any tool — or even help define new flows. EDA tools are built to be shaped. But only when your design thinking is too. Let’s make design intelligence the real differentiator. #SemiconductorSimplified #ASICDesign #RTLDesign #VLSI #ChipDesign #EDA #CareerInSemiconductors #WebinarAlert

36

1 Comment

🟡🟡🟡FPGA Vs ASIC🟡🟡🟡 1) Customization: 🔹FPGA: Programmable logic blocks allow for reconfigurability. 🔹ASIC: Fixed circuitry designed for specific tasks. 2) Time to Market: 🔹FPGA: Faster development due to pre-existing components. 🔹ASIC: Longer development time for custom designs. 3) Cost: 🔹FPGA: Higher initial cost but lower upfront investment. 🔹ASIC: Lower unit cost for mass production but higher initial investment. 4)Performance: 🔹FPGA: Flexible but generally lower performance compared to ASIC. 🔹ASIC: Highly optimized for specific tasks, leading to superior performance. 5) Power Consumption: 🔹FPGA: Generally higher power consumption due to reconfigurability. 🔹ASIC: Lower power consumption due to optimized design. 6) Flexibility: 🔹FPGA: Highly flexible with the ability to reconfigure for different applications. 🔹ASIC: Fixed functionality, offering limited flexibility. 🔗Conclusion: 🔹Choosing between FPGA and ASIC depends on project requirements, budget, and long-term goals. 🔹Understanding these key differences is crucial for selecting the most suitable technology for your application. #India #Innovation #Technology #Creativity #VLSI #Future #Futurism #Entrepreneurship #motivation #education #engineering #mindfulness

16

Intel Corporation’s recent updates caught my attention. Their 18A process is entering risk production, which is a promising sign for their RibbonFET and PowerVia technologies. They are aiming to reach parity with TSMC at the 1.8nm level by the second half of 2025. Early reports suggest yields are around 50 percent, with reasonable defect levels, indicating that the process is starting to stabilize. On the business side, Intel Foundry Services has reportedly secured the GPU deal for Nintendo’s upcoming Switch 3 with an estimate of $8B in revenue. It may not be a major data center GPU win, but it is still a meaningful step for a foundry that is working to prove itself. Is Intel turning a corner, or will TSMC stay ahead at 2 nanometers? Curious to hear your perspective. #Intel #TSMC #semiconductor

140

2 Comments