Denis Brockus

*** Silent Killer in High-Speed Interface Design *** Every engineer working on PCIe, USB, CSI, DSI, LPDDR, SerDes, or any high-speed interface knows: "Timing closure will keep you Up at night." But here’s the thing—It is not always the big violations that kill a design. These can be found and fixed. The silent killers are the marginal cases: * That one Async Clock Domain Crossing that looked fine… until Silicon. * That Power mode Transition that only happens under rare Conditions. * That Corner case in Equalization that only fails in a specific voltage/temp combo. "These don’t show up in the standard verification flow. You have to hunt them down." What’s your approach to catching these hidden pitfalls?

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Intel Corporation 18A is now in high-volume production at Fab 52. Let that sink in. This is the first 2nm-class node developed and manufactured in the United States. Not a roadmap. Not a promise. Production. Here's my take: A lot of people have written Intel off. Too slow. Too late. Can't compete with TSMC. I've heard it all. But I've also spent 28 years in fabs, and I know what it takes to pull something like this off. It's not just engineering it's sheer will. Does Intel still have work to do? Absolutely. But anyone who thinks this moment doesn't matter isn't paying attention. The U.S. now has a credible path to leading-edge manufacturing again. That changes the conversation. 2025 was the year Intel had to prove it could execute. 2026 is the year we find out if the market believes them. I'm watching closely. #Semiconductors #Intel #Manufacturing #ChipsAct #SupplyChain

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🚀 Socionext Breaks New Ground with 3DIC & 5.5D Packaging Socionext has officially taped out a next-gen SoC using TSMC’s SoIC-X 3D stacking—combining N3 compute and N5 I/O dies in a face-to-face (F2F) configuration. This milestone slashes latency, boosts bandwidth, and cuts power consumption, redefining what's possible in consumer, AI, and HPC applications. With support for chiplets, 2.5D, 3D, and now 5.5D packaging, Socionext is leading the charge in heterogeneous integration—bringing together multiple tech nodes and functions in a single, high-density package. 🔧 Vertical stacking. ⚡ Lower power. 📦 Smaller footprint. 💡 Limitless potential. #Semiconductors #3DIC #SoC #Innovation #Socionext #TSMC #AI #HPC #ChipDesign #TechLeadership #Hiring #Semiconductorhiring #ASIC #Marketing #TPM #Technicalprogrammanager(s) #SFBAYAREAJobs

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Power, performance, and possibilities 🤝 Lattice’s award-winning FPGA platforms: Lattice Avant, Lattice Nexus, and Lattice Nexus 2. View the links in the comments to discover how each FPGA platform delivers optimized compute, low power consumption, and scalability for next-generation applications.

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Data center bandwidth limits are a thing of the past. 🚧 The massive demands of A.I. and GPU computing require a breakthrough. Our new post breaks down how PCIe Gen 7 PHY delivers the performance, reliability, and power savings needed to transform compute, storage, and networking. 128 GT/s is the new standard. Read Full Blog Here: https://lnkd.in/gGFgc_pu #AIComputing #HPC #PCIe #Bandwidth #Technology

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I’m building an RF Generator. Something useful for my workbench and beyond, and also a way to keep myself in RF “shape.” It’s designed to deliver about 70–80% of what a full benchtop RF generator can do, but at just a fraction of the cost. The plan is an aluminum enclosure with an LMX2572 and AD9833, so it can generate CW tones from basically DC (ok, kHz) up to 6.4 GHz. Power and control will come through a modern USB-C connector. On board I’ll use a Renesas RA4M1 MCU (same as the Arduino Nano R4). It will handle the digital step attenuator and gain blocks, giving me an 80 dB power control range. Once (and if...) I manage to flash the Arduino bootloader, I’ll be able to pull in Arduino libraries and quickly put together SPI sketches for all the chips. I’m debating two things: ◾ LMX2572 has two RF outputs. Should I:  • Expose two independent outputs?  • Add an internal mixer so this box can double as an up/down-converter?  • Throw in a doubler to push the second output up toward 12 GHz? ◾ USB-C power. Do I need a PD sink controller? Not sure yet. Once I nail down total power consumption, I’ll know. For robustness, every I/O line will have ESD protection, and power rails will have over-voltage / over-current protection.

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Launch DevDuck, Bob, and your cloud-hosted Llama 4 Scout agent — all in one go with a simple Docker compose up. We are partnering with Docker, Inc to bring you Container-Native Multi-Agent AI. Powered by Cerebras wafer-scale inference (~2,600 tok/s) and Google’s Agent Development Kit. Try the demo today, scale in production tomorrow. Clone the repo: https://lnkd.in/g3V7huYZ

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Confused between Testbench, Testcase, Testplan, TestID, Test PASS/FAIL etc.? Here’s a quick guide with real-world SoC-level relevance ⬇️ Imagine you're working on verifying a USB 3.0 controller in a System-on-Chip (SoC). Here's how these terms come alive: 🔹 Testbench – Your full verification environment with agents, drivers, monitors, and DUT instantiation. This simulates USB traffic. 🔹 Testcase – A specific stimulus like "bulk data transfer test" to check performance under load. 🔹 Test Scenario – Real-world use case like "file transfer from mobile to PC". 🔹 Testplan – Includes goals like data integrity checks, protocol compliance, error injection cases, etc. 🔹 Test ID – Maps to each test in the test management tool, helps traceability. 🔹 Test Result – Captures whether each scenario passed or failed, enabling bug triage and coverage closure. 🧠 Advanced Questions for Pros: 1. How do you structure a layered UVM testbench for SoC-level IP integration? 2. What’s your approach to reuse UVM components across IP, Subsystem, and SoC levels? 3. How do you perform stimulus generation for asynchronous clock domains in SV? 4. What strategies do you follow to ensure maximum functional coverage in constrained-random verification? 5. How do you debug issues that appear only in gate-level simulation but not in RTL? Join us and shape your future in VLSI! Our website : https://provlogic.com/ 👉 The Best Training Program for Working Professionals Looking to Lead in VLSI! 👉 For more information do contact ProV Logic or Prasanthi Chanda #mentor #guidance #training #workshop #vlsi #internships #design #verification #masters #interview #physicaldesign #vlsidesign #coaching #chip #manufacturing #digital #analog #semiconductor

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FPGA or DSP—which one truly fits your performance and flexibility needs? From processing performance and power efficiency to development complexity, cost, and real-world applications, this blog breaks down the key differences to help you make the right design choice. 👉 Read the complete blog to understand which technology aligns best with your next design challenge - https://lnkd.in/di-VXbww #FPGA #DSP #EmbeddedSystems #SignalProcessing #HardwareDesign #SystemArchitecture #EngineeringInsights #TechBlog

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Ashling today announced full debug and trace support for Tenstorrent’s Ascalon RISC-V CPU within its RiscFree SDK. TT-Ascalon is Tenstorrent’s high-performance RISC-V CPU, built on open standards to provide maximum flexibility and architectural control. It is based on the open RISC-V ISA and is RVA23 compliant. A central focus of the Ashling–Tenstorrent collaboration is comprehensive trace support, built on the RISC-V standard N-Trace architecture. RiscFree integrates with Tenstorrent’s Ascalon CPUs to capture detailed trace data across multi-core systems, enabling real-time visibility into instruction execution, memory transactions, and key system events. In addition to N-Trace, Tenstorrent’s Debug Signal Trace (DST) infrastructure has been fully implemented in its Ascalon CPUs, providing access to critical micro-architectural signals alongside standard trace data during post-silicon validation. DST enhances debugging, performance analysis, and coverage, and is fully supported by Ashling’s RiscFree tools—enabling deep trace visibility with minimal integration overhead. Learn more here: https://lnkd.in/gthF_9uj #RISCVEverwhere #DEBUG #Tenstorrent

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A compact, practical field-guide to CDC (Clock Domain Crossing)—what it is, why it bites, and proven design/verification patterns that actually work. What is CDC and why it’s hard When a signal produced by one clock domain is sampled by another unrelated (asynchronous/plesiochronous/mesochronous) clock, it can violate setup/hold at the receiving flop and enter metastability. You can’t eliminate metastability; you only reduce its probability to an acceptably low level and prevent bad fanout/glitches/reconvergence from turning one metastable event into many. Core concepts (quick glossary) • Asynchronous domains: No fixed phase/frequency relation. Needs full CDC handling. • Mesochronous: Same nominal frequency, unknown phase. Treat as async unless you have a guaranteed phase relationship. • Plesiochronous: Nearly same frequency but with drift. Treat as async. • Metastability parameters: τ (time constant of the receiving flop) and T₀ (device-dependent). • MTBF (mean time between failure): Roughly MTBF ≈ exp((Tres − T₀)/τ) / (Fclk · Ftoggle) Increase resolution time (extra sync stages), slow data toggle rate, or use faster flops to push MTBF >> product lifetime. What crossings exist (and what to use) 1. 1-bit level (slowly changing)- Metastability-2-flop (or 3-flop) synchronizer in destination clock 2. 1-bit pulse, src slower than dst- Pulse can be missed-2-flop + edge detect in dst, or stretch pulse in src 3. 1-bit pulse, src faster than dst-Pulse often missed-Toggle synchronizer or req/ack handshake 4.Multi-bit control (correlated bits)-Bit-skew; illegal combos-Encode to one-hot/Gray, or pass data + valid with handshake 5.Multi-bit data stream-Coherency & throughput-Asynchronous FIFO with Gray-coded pointers 6.Cross-domain resets-Deassertion metastability-Synchronous deassertion per domain; RDC checks 7. Source-synchronous buses-Skew, phase drift-Capture with forwarded clock, then re-sync to local clock 8.Cross-clock enables/gates-Glitch propagation-Generate enables locally after sync; avoid comb logic on CDC path Asynchronous FIFO (throughput workhorse) • Dual-clock RAM. • Write pointer (src clk) and read pointer (dst clk). • Convert binary pointers → Gray code before sending across; synchronize Gray pointers (2-flop) at the other side. • Empty/Full compare in the local domain using the remote pointer that has been Gray-synced. Timing & constraints (STA/SDC hygiene) • Declare async clocks: set_clock_groups -asynchronous -group {clk_src} -group {clk_dst} • Cut CDC data paths to avoid meaningless timing violations: set_false_path -from [get_clocks clk_src] -to [get_clocks clk_dst] • For multi-bit Gray buses (FIFO pointers), constrain skew so all bits arrive within <= one destination clock: • Use set_max_delay -datapath_only or set_bus_skew between pointer flop Qs (src) and sync inputs (dst). • Don’t put combinational logic between synchronizer stages. • Place the two synchronizer flops physically close (same cell row)

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What does acceleration feel like to an engineer? On the left: hours lost to data prep and workflow restarts. On the right: that time reclaimed for modeling, testing, and shipping. Faster hardware doesn’t just cut tasks, it changes the shape of your day. Chapter 4 of The Codex report walks through the math and the culture shift that follows. 🔗https://lnkd.in/gGXhxe78 #theseus #VoltronData

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Engineering teams are being asked to do more with less. 📘🔧 More complex FPGA logic. More firmware. More compliance. Tighter schedules. Smaller teams. ⚙️ At a certain point, adding hours is no longer enough. Leaders need a strategic way to expand capacity without compromising architecture, IP, or delivery timelines. 📈 We just published a new field guide that explains how senior engineering teams scale the right way. It covers the signals that external support is needed, the engagement models that actually accelerate delivery, and the hidden costs that often go unnoticed. If you are responsible for complex systems and demanding roadmaps, this guide delivers clear, practical direction. 👉 Read now: https://lnkd.in/eGfhTkrH #EmbeddedSystems #FPGADesign #ProductDevelopment #SystemIntegration #HardwareDesign

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MIPS delivers industry-leading, scalable RISC-V processor IP designed to orchestrate data movement for Physical AI workloads. The I8500 provides deterministic, low-latency performance optimized for real-time embedded applications across automotive gateways, industrial IoT, communications infrastructure, and aerospace systems.

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