Gilberto Migliorin

It's an exciting time at Texas Instruments as we announce an award agreement of up to $1.6B in direct funding through CHIPS for America, which will support three new fabs under construction in Sherman, Texas, and Lehi, Utah. https://lnkd.in/g_6bc4Tp ​

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It's an exciting time at Texas Instruments as we announce an award agreement of up to $1.6B in direct funding through CHIPS for America, which will support three new fabs under construction in Sherman, Texas, and Lehi, Utah. https://lnkd.in/gYTcf_FF ​

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𝗧𝗼 𝗘𝘃𝗲𝗿𝘆𝗼𝗻𝗲 𝗪𝗵𝗼 𝗕𝘂𝗶𝗹𝗱𝘀 𝗦𝗶𝗹𝗶𝗰𝗼𝗻 ➖ "𝗖𝗵𝗶𝗽 𝗪𝗮𝗿" 𝗜𝘀 𝘁𝗵𝗲 𝗦𝘁𝗼𝗿𝘆 𝗬𝗼𝘂 𝗖𝗮𝗻’𝘁 𝗔𝗳𝗳𝗼𝗿𝗱 𝘁𝗼 𝗠𝗶𝘀𝘀 I just finished Chris Miller’s Chip War, and it hit differently when you’ve spent years chasing timing closure, debugging DRCs, or optimizing for PPA. We often see our work as purely technical, but this book reframes it entirely. It reminds us that we’re not just designing circuits; we’re building the foundation of global power. 🌍 𝗦𝗶𝗹𝗶𝗰𝗼𝗻 𝗧𝗵𝗲 𝗡𝗲𝘄 𝗢𝗶𝗹 𝗼𝗳 𝘁𝗵𝗲 𝟮𝟭𝘀𝘁 𝗖𝗲𝗻𝘁𝘂𝗿𝘆 In a world increasingly reliant on technology, the importance of semiconductors cannot be overstated. Every smartphone, car, satellite, and defense system depends on these tiny pieces of silicon the invisible engines driving our digital age. After diving deep into Chris Miller's "Chip War," I've come to realize: whoever controls chip manufacturing controls the future. 𝗧𝗵𝗲 𝗠𝗼𝘀𝘁 𝗣𝗼𝘄𝗲𝗿𝗳𝘂𝗹 𝗣𝗮𝗿𝘁𝗻𝗲𝗿𝘀𝗵𝗶𝗽 𝗬𝗼𝘂'𝘃𝗲 𝗡𝗲𝘃𝗲𝗿 𝗛𝗲𝗮𝗿𝗱 𝗢𝗳 Two companies. Two countries (Netherlands & Taiwan). One irreplaceable partnership. Without ASML's $350 million EUV lithography machines the most complex devices ever built advanced chips simply cannot exist. Only one company manufactures them. Without TSMC's manufacturing mastery, those machines are useless. Only one company can turn silicon into 3nm miracles at scale. Here's the reality: Every AI breakthrough, every smartphone, every advanced weapon system passes through these two companies. Not Google. Not Apple. Not even America or China can bypass them. 90%+ of the world’s advanced logic chips (<7nm) come from a single company on a single island. the quiet powerhouse that fabricates world’s most advanced chips. Whether your design’s at 5nm, 3nm, or the upcoming 2nm GAA odds are, it’s going to TSMC. 𝗧𝗵𝗲 𝗜𝗻𝗱𝗶𝗮 𝗔𝗻𝗴𝗹𝗲 India’s story feels different this time: 𝗙𝗮𝗯𝘀 𝗮𝗿𝗲 𝗰𝗼𝗺𝗶𝗻𝗴 (Micron ATMP, Tower partnership, Tata proposals) 𝗗𝗲𝘀𝗶𝗴𝗻 𝗲𝗰𝗼𝘀𝘆𝘀𝘁𝗲𝗺 is already World Class 𝗧𝗮𝗹𝗲𝗻𝘁 𝗽𝗶𝗽𝗲𝗹𝗶𝗻𝗲 is deep we just need manufacturing scale This could redefine local tape outs, reduce timezone bottlenecks, and open global opportunities from Indian soil. India's immediate success is not about competing with TSMC at the 2nm edge. It is about establishing resilient domestic capacity in crucial mature and specialty nodes for automotive, power, communications and industry automation. which currently accounts for the bulk of India’s import demand while simultaneously investing heavily in the R&D and talent needed to close the advanced node gap over the next decade. 💭 I’d like to hear your thoughts. #ChipWar #SemiconductorIndustry #VLSI #TechGeopolitics #SemiconIndia #SiliconPower #ChipDesign #FutureOfTech

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“In recruitment, speed without clarity is wasted effort.” In semiconductor hiring, profile count is irrelevant. What truly matters is quality of profiles—engineers who match the exact node, tools, and responsibilities required. I’ve seen this consistently: the fastest closures don’t come from pushing hundreds of resumes. They come from well-defined requirements and technical alignment at the start. When clarity is in place, everything flows naturally—candidates feel respected, managers see precision, and recruiters earn trust as true partners. This isn’t a new lesson—it’s a principle I’ve carried throughout my career, and it has shaped how I lead teams and mandates globally. #Leadership #TalentAcquisition #Semiconductors #VLSI #RecruitmentExcellence #FutureOfWork

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Texas Instruments Faces Prolonged Market Headwinds Amid Tariff and Demand Uncertainty Shares of Texas Instruments (TI) fell 6% on Wednesday following a downbeat fourth-quarter forecast, signaling extended weakness in the analog chip market. The company expects Q4 revenue of $4.4 billion and earnings per share of $1.26, both below analyst estimates. Despite TI’s $60 billion investment in expanding U.S. manufacturing, the rebound in analog demand remains subdued. Analysts cite an uncertain global economy, cautious industrial spending, and unresolved U.S.–China tariff rules as key headwinds. Brokerages including Jefferies and Charter Equity Research warn softness could persist across the analog sector, with 16 firms lowering TI’s price targets. If losses hold, TI stands to lose about $10 billion in market value. Competitors ON Semiconductor, NXP Semiconductors, and Analog Devices also saw shares drop 2–3%, reflecting broader investor concerns over prolonged inventory and margin pressures. How might the evolving tariff landscape and industrial spending trends shape analog chip recovery in 2025? Thanks to Reuters for providing the full article with additional background, charts, and insights at the link below. 👇 https://lnkd.in/gYjKmUdZ #ChipDesign,#SemiconductorManufacturing, #VLSI, #Lithography, #ICPackaging

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🟡🟡🟡FPGA Vs ASIC🟡🟡🟡 1) Customization: 🔹FPGA: Programmable logic blocks allow for reconfigurability. 🔹ASIC: Fixed circuitry designed for specific tasks. 2) Time to Market: 🔹FPGA: Faster development due to pre-existing components. 🔹ASIC: Longer development time for custom designs. 3) Cost: 🔹FPGA: Higher initial cost but lower upfront investment. 🔹ASIC: Lower unit cost for mass production but higher initial investment. 4)Performance: 🔹FPGA: Flexible but generally lower performance compared to ASIC. 🔹ASIC: Highly optimized for specific tasks, leading to superior performance. 5) Power Consumption: 🔹FPGA: Generally higher power consumption due to reconfigurability. 🔹ASIC: Lower power consumption due to optimized design. 6) Flexibility: 🔹FPGA: Highly flexible with the ability to reconfigure for different applications. 🔹ASIC: Fixed functionality, offering limited flexibility. 🔗Conclusion: 🔹Choosing between FPGA and ASIC depends on project requirements, budget, and long-term goals. 🔹Understanding these key differences is crucial for selecting the most suitable technology for your application. #India #Innovation #Technology #Creativity #VLSI #Future #Futurism #Entrepreneurship #motivation #education #engineering #mindfulness

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The design of high-bandwidth PCB-RCs is discussed using the frequency response characteristics of the sensor, incorporating OP-AMP non-idealities. Continuous time-domain subtraction of the device currents is achieved with an instrumentation amplifier stage to reconstruct the AC node current. By virtue of the inherent isolation offered by PCB-RCs, the reconstructed current is directly coupled with an ADC channel of the microcontroller for subsequent closedloop current control. Further, using the developed PCB-RCs, ultrafast short-circuit protection for the GaN HEMTs is achieved under a DC bus fault at 400 V.

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Update - NEW SILICON PARETO CURVE, EVP: It’s been 8 months since I first posted about the concept of EVP: "I've debated this problem for a while, and many people have looked at replacing the infamous PPA Pareto curve. I have experimented with adding interconnects (including the pins) to the equation, as well as 4-letter and 5-letter replacements. After playing with several alternatives, I think EVP is probably the most effortless future transition and more straightforward to pronounce than the alternatives.” ** ENERGY, E: because our community should care not only about Performance but the "cost" of Performance, i.e., energy-in and the heat-out. Power does not accurately reflect the cost. Yes, time is a function of Performance, but it is also a function of cost. I am concerned that the industry has lost its Moral Imperative on efficiency. Reduction of logic or geometry shrinkage is a minor factor in the efficiency game and not particularly useful (2025 update, giving us 3% to 5% per shift). ** VOLUME, V: Yes, we will be moving to physical 3D silicon, no longer concerned with 2D floorplans (very 1970s). We will choose computational cubes over pancakes. We will care more about making 3D circuits cool enough to drive future computational cubes that avoid thermal nuclear meltdowns. ** PERFORMANCE, P: does not change. Performance is the metric for a satisfied consumer. Again, linked to Energy, but how much is too much? How close can we push the modern computing world towards the Margolus-Levitin limit with the available Energy without destroying the world's resources in the process?" 2025 UPDATE: That was my initial thought on replacing PPA, but there is a more fundamental consideration as well: we need to escape Euclidean geometry (2D). Yes, FinFETs and GAA transistors are 3D, but the design of logic remains 2D.  Tensors, Vectors, and Quaternions (plus alternatives) aren’t just crucial for Artificial Intelligence; they will be essential for future silicon computational design. #VaireComputing #AdiabaticReversibleComputing #PhysicsAwareComputing #NearZeroEnergyChips #Physics #Semiconductor #Future #PPA #EVP

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Silicon Labs just announced the FG23L, the latest addition to our Series 2 portfolio. Dev kits are available now and full GA is set for September 30. FG23L brings long-range sub-GHz connectivity, ultra-low power, and built-in security at a fraction of the cost of comparable solutions. It’s designed for applications like industrial sensors, smart cities, and building automation where range, efficiency, and cost all matter.

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Is VLSI Talent Acquisition still seen as a cost center in 2025? Let’s change that. Every chip company wants the best ASIC, SoC, and Firmware talent. But not every company treats hiring as a strategic function. Too often, I see: 🔸 Hiring plans driven by urgency—not roadmap alignment 🔸 Recruiters chasing unrealistic timelines without clear JD-to-skill mapping 🔸 Interviewers chosen by availability, not capability 🔸 Offers made before stakeholder calibration is complete But when hiring works—it changes everything: 💥 Execution speed 💥 Team morale 💥 Retention 💥 Tapeout timelines So why are TA leaders still fighting for a seat at the table? If 2025 is the year of GenAI and semiconductor resurgence— It must also be the year TA becomes a business partner, not a backend service. What I believe: ✅ Every headcount should tie back to silicon delivery KPIs ✅ TA should sit with engineering leadership—not behind them ✅ Interviews should be structured like design reviews: consistent, data-backed, and outcome-driven Talent drives silicon. TA should drive strategy. If you're in TA, HR, or leadership in the VLSI space—what’s still holding us back from making this shift? Let’s start the conversation. 💬 #VLSI #Semiconductor #TalentAcquisition #HiringStrategy #Leadership #GenAI #TapeoutSuccess #RecruitingReimagined

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𝐇𝐨𝐰 𝐭𝐡𝐞 𝐀𝐠𝐞 𝐨𝐟 𝐒𝐞𝐦𝐢𝐜𝐨𝐧𝐝𝐮𝐜𝐭𝐨𝐫 𝐂𝐨𝐦𝐩𝐚𝐧𝐢𝐞𝐬 𝐌𝐚𝐩𝐬 𝐭𝐨 𝐌𝐚𝐫𝐤𝐞𝐭 𝐕𝐚𝐥𝐮𝐞  Source: Thanks to Nader EL-Masri for positing it on LinkedIn An insightful snapshot of the #semiconductor industry—showing how company age, type, and value intersect. • Legacy leaders like #Samsung, #Intel, and #Texas Instruments were founded decades ago—and still dominate. • Younger giants like #NVIDIA and #TSMC have surged to the top in market value. Worth noting #Nvidia now leads the pack in market cap—surpassing peers founded 30–50 years earlier! • Fab and Logic companies are driving the majority of value creation today. • Specialized players like #ASML, #Arm, and #AnalogDevices show niche focus can scale. Only a few public #semiconductor companies have emerged in the space of 20 years. Despite explosive industry #growth & tripling in value. 💡 #Semiconductors #TSMC #NVIDIA #EDA #Fabless #Chips #TechTrends

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TI & Silicon Labs: a strategic move reshaping the embedded & wireless landscape Texas Instruments and Silicon Labs announced that they have signed a definitive agreement under which Texas Instruments will acquire Silicon Labs for $231.00 per share in an all-cash transaction, representing a total enterprise value of approximately $7.5 billion. Why this acquisition matters? Because #wireless connectivity is one of the fastest-growing opportunities in #embedded processing. And Silicon Labs brings exactly what TI was missing: strong, secure wireless platforms including #Bluetooth, Wi-Fi, #Zigbee, Thread, Matter. And that perfectly complement TI’s analog and #RF strengths. A very big thank you to Thomas Hackenberg and Yole Group for their "DECODE" of this transaction via the link below and their full article 🙏💡👇 https://lnkd.in/dauRPkjH #semiconductorindustry #semiconductor #semiconductors #it #tech #ic #iot #embeddedsystem #technology #geopolitics #innovation #chips #it #infineon #nxp #renesas #st

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If you’re working on space-constrained designs, high-density power delivery is likely top of mind. Analog Devices January Power Newsletter shares practical insights on how integration can simplify design while maintaining performance and reliability: https://bit.ly/3ZCZNat

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Has anyone noticed that chip designers think that AI will reduce verification costs while chip verifiers think that AI will reduce design costs? 🤔 Wouldn't it be great if AI reduced management?

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AI isn’t slowing down, and Broadcom continues expanding its optical interconnect solutions portfolio for next-gen AI infrastructure. Today, we’re proud to announce the expansion of our industry-leading 200G/lane DSP PHY portfolio with the introduction of Sian3 and Sian2M, purpose-built for the demanding connectivity requirements of AI/ML clusters. Learn more: https://dy.si/HM9MHj2

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