Anton Lawrendra

I have been hearing from multiple hiring managers at semiconductor companies that what they look for in senior engineers is starting to change: The "most wanted" engineers today don’t fit perfectly into “hardware” or “software.” They are "hybrids". People who understand chip design and materials, but also know how software, AI models, and data interact with that hardware. Some will say, “that’s nothing new, hardware and software have always worked together.” Of course that is true, but the two areas are much more linked now I am starting to see. It’s not just about firmware anymore. So are chip designers starting to use AI tools to help design chips automatically. For example, using machine learning to optimise chip layouts or reduce power consumption. Big EDA vendors (Synopsys, Cadence) are adding AI capabilities to their tools. They use machine learning to speed up or improve tasks like verification, layout, power/performance/area tradeoffs, and error checking. DeepMind has developed a reinforcement-learning based system that generates chip layouts. The system can design layouts in hours that would normally take weeks. Their layouts have been used (or claimed to be used) in Google’s TPU chips. An other example: System engineers are designing hardware architectures (how the chip is structured) based on how AI models perform. This basically means the hardware is being built to match what AI models need. The integration is now at the core of how products are built. You can see this across the industry: * Nvidia blends hardware and AI expertise in the same teams. * ASML hires engineers who combine optics with data analytics. * Smaller design houses want verification engineers who can script and use AI tools. McKinsey projects the semiconductor industry will need over a million additional skilled workers by 2030, many in roles that blend hardware and software. But many companies still hire as if these disciplines were separate. From my conversations with industry experts, it’s clear that the next generation of AI-enabled chips will depend on teams who understand both sides. With that in mind, if you’re hiring, it might be time to rethink what makes someone qualified. I always suggest to look for curiosity, adaptability, and engineers who’ve worked across layers. Even if their background isn’t a perfect match. From my point of view, these hybrid engineers will make future products possible.

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For Embedded Engineers considering a move in 2026, a few honest observations from the market. The strongest engineers I speak to are not the ones who know every RTOS or MCU family. They are the ones who can explain why a system was architected a certain way, how they handled failure modes, and what tradeoffs they made under real constraints. What is coming up repeatedly in interviews right now Ownership of firmware architecture, not just feature delivery Clear experience with real hardware bring up and debugging Comfort working cross functionally with EE and Mechanical teams The ability to talk through decisions, not just list tools On the flip side, the best companies are Having engineers interview engineers Keeping technical panels practical, not academic Being clear on impact, scope, and expectations early If you are evaluating opportunities this year, focus less on job titles and more on ownership, decision making, and the problems you will actually be trusted to solve. In the end, the engineers who stand out are the ones trusted with decisions, not just code. #beUneek #EmbeddedEngineers #Embedded

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Is VLSI Talent Acquisition still seen as a cost center in 2025? Let’s change that. Every chip company wants the best ASIC, SoC, and Firmware talent. But not every company treats hiring as a strategic function. Too often, I see: 🔸 Hiring plans driven by urgency—not roadmap alignment 🔸 Recruiters chasing unrealistic timelines without clear JD-to-skill mapping 🔸 Interviewers chosen by availability, not capability 🔸 Offers made before stakeholder calibration is complete But when hiring works—it changes everything: 💥 Execution speed 💥 Team morale 💥 Retention 💥 Tapeout timelines So why are TA leaders still fighting for a seat at the table? If 2025 is the year of GenAI and semiconductor resurgence— It must also be the year TA becomes a business partner, not a backend service. What I believe: ✅ Every headcount should tie back to silicon delivery KPIs ✅ TA should sit with engineering leadership—not behind them ✅ Interviews should be structured like design reviews: consistent, data-backed, and outcome-driven Talent drives silicon. TA should drive strategy. If you're in TA, HR, or leadership in the VLSI space—what’s still holding us back from making this shift? Let’s start the conversation. 💬 #VLSI #Semiconductor #TalentAcquisition #HiringStrategy #Leadership #GenAI #TapeoutSuccess #RecruitingReimagined

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Hiring patterns changed. RAM prices explained. Hiring strategy across semiconductor companies has quietly shifted. 1. Less generic VLSI hiring 2. More demand for HBM & memory architecture experts 3. High-speed interfaces & advanced packaging 4. Bandwidth, power, and performance specialists That was the first signal. Then came my deductions AI doesn’t just need compute — it needs memory bandwidth. So memory companies shifted capacity from commercial DRAM to HBM for data centers and AI accelerators. What followed was inevitable: Less commercial RAM supply Same demand Higher prices everywhere This isn’t inflation. This is AI-driven prioritization. Your laptop RAM is now competing with AI data centers. And AI always wins. Strategic shift by memory vendors Slowing consumer & commercial DRAM Aggressively pushing HBM for AI & data centers Fewer wafers for PCs, phones, laptops More capacity reserved for high-margin HBM stacks Result? Even regular RAM feels expensive. Hiring patterns tell the future before prices do. Watching how the HBM ecosystem evolves across memory, foundry, and AI platforms. SK hynix / Samsung Electronics / Micron Technology / NVIDIA / AMD / Intel Corporation / TSMC / Amkor Technology, Inc. / ASE Global 💬 Curious to hear from memory, SoC, and system architects — Is HBM the biggest silent disruptor of this decade?

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*** Silent Killer in High-Speed Interface Design *** Every engineer working on PCIe, USB, CSI, DSI, LPDDR, SerDes, or any high-speed interface knows: "Timing closure will keep you Up at night." But here’s the thing—It is not always the big violations that kill a design. These can be found and fixed. The silent killers are the marginal cases: * That one Async Clock Domain Crossing that looked fine… until Silicon. * That Power mode Transition that only happens under rare Conditions. * That Corner case in Equalization that only fails in a specific voltage/temp combo. "These don’t show up in the standard verification flow. You have to hunt them down." What’s your approach to catching these hidden pitfalls?

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🚀 Socionext Breaks New Ground with 3DIC & 5.5D Packaging Socionext has officially taped out a next-gen SoC using TSMC’s SoIC-X 3D stacking—combining N3 compute and N5 I/O dies in a face-to-face (F2F) configuration. This milestone slashes latency, boosts bandwidth, and cuts power consumption, redefining what's possible in consumer, AI, and HPC applications. With support for chiplets, 2.5D, 3D, and now 5.5D packaging, Socionext is leading the charge in heterogeneous integration—bringing together multiple tech nodes and functions in a single, high-density package. 🔧 Vertical stacking. ⚡ Lower power. 📦 Smaller footprint. 💡 Limitless potential. #Semiconductors #3DIC #SoC #Innovation #Socionext #TSMC #AI #HPC #ChipDesign #TechLeadership #Hiring #Semiconductorhiring #ASIC #Marketing #TPM #Technicalprogrammanager(s) #SFBAYAREAJobs

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10 Steps to Make a Chip (as Building a City) 1. Sand to Silicon Ingot → Choosing the Land Just like a city starts with a flat piece of land, chips begin with purified silicon from sand. The silicon ingot is like the bedrock foundation on which everything else will be built. 2. Wafer Slicing → Cutting City Plots Imagine slicing that land into perfect plots for development. Wafers are those plots: smooth, uniform "real estate" for our future skyscrapers (transistors). 3. Wafer Cleaning → Clearing the Land Before construction, you remove weeds, rocks, and dust. Wafers get an ultra-deep cleaning, since even a tiny speck is like a boulder in our micro-city. 4. Oxidation → Laying the Roads Cities need roads before buildings. The silicon dioxide insulation is like the roads and pavements, guiding traffic and keeping buildings apart. 5. Photolithography → Blueprints & Construction Permits Architects use blueprints to decide where buildings go. Masks in lithography are those blueprints, projected onto the wafer using light. Photoresist is like construction chalk on the ground. 6. Etching → Excavating the Foundations Bulldozers dig out where buildings will rise. Etching removes unwanted material, carving out plots for skyscrapers (the transistors). 7. Doping → Wiring the City with Power & Water A city needs electricity, plumbing, and gas lines. Doping injects impurities into silicon, creating wiring channels (n-type and p-type) so electrons (citizens) can move in. 8. Deposition & Metallization → Building Skyscrapers & Highways Skyscrapers (transistors) rise floor by floor. Metal layers are like highways and flyovers, connecting every building so the city works together. 9. Polishing (CMP) → Leveling the Terrain After each district is built, you flatten the land again before starting the next. Keeps the city skyline balanced, layer by layer, until it’s a mega-metropolis. 10. Testing, Dicing & Packaging → City Opening Ceremony Inspect every building to make sure it’s safe. Cut the city blocks into separate mini-cities (chips). Wrap each one with protective walls and gates (packaging). Now, citizens (electrons) can move in and live happily ever after in the silicon city! ⚡ A microchip is basically a tiny city with billions of skyscrapers (transistors), highways (interconnects), and traffic (electrons). ~~~~~ If you are looking to invest in semiconductors and looking for expert insights, drop us a DM.

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$100K H-1B Fee Could Trigger Perfect Storm in Already-Strained Semiconductor Workforce The semiconductor industry just got hit with a potential game-changer. New H-1B visa fees of $100,000 annually could severely impact an industry already facing its worst talent crisis in decades. The Stark Reality:  67,000 unfilled semiconductor engineering positions projected by 2030 (Semiconductor Industry Association)  71% of H-1B beneficiaries come from India, where many chip design engineers originate  $300,000 total cost per H-1B employee over 3-year visa period under new rules  85,000 H-1B visas distributed annually, with tech sector as primary beneficiary Why This Matters Now: The U.S. semiconductor industry is in a race against time. We’re building new fabs worth hundreds of billions while simultaneously facing acute shortages in: ▪️ Advanced circuit design engineers ▪️ Process development specialists ▪️ Equipment integration experts ▪️ AI/ML chip architects The Domino Effect: With major tech companies like Amazon (10,000+ H-1B visas) and Microsoft (5,000+ visas) already stretching budgets, smaller semiconductor startups and mid-tier companies may be priced out entirely. Critical Questions: → Will companies accelerate offshore R&D to access talent? → Can domestic STEM programs scale fast enough to fill gaps? → How will this impact U.S. competitiveness against China’s semiconductor ambitions? What’s at Stake: This isn’t just about immigration policy—it’s about maintaining America’s technological edge in the most strategic industry of our time. The decisions made in boardrooms over the next 6 months could reshape the global semiconductor landscape for decades. The clock is ticking. The talent war just got exponentially more expensive. What strategies is your organization considering to navigate this new reality? #SemiconductorCrisis #TalentShortage #ChipIndustry #H1BVisa #TechWorkforce #Innovation #STEM

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It's an exciting time at Texas Instruments as we announce an award agreement of up to $1.6B in direct funding through CHIPS for America, which will support three new fabs under construction in Sherman, Texas, and Lehi, Utah. https://lnkd.in/gYTcf_FF ​

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📺 Ever wondered where PWM or PDM is actually used in real life? Most of us remember learning about modulation techniques like PWM (Pulse Width Modulation) or PDM (Pulse Density Modulation) in our embedded systems classes... ...and then we forgot them. Not because they’re useless, but because no one told us where they really shine. 🎯 One underrated yet daily use-case? Your TV or AC Remote. Yes, seriously. Every time you press a button to change the channel or switch off the AC, you're unknowingly triggering a PWM-based communication. 🔍 So How It Works: Infrared (IR) remotes use modulation techniques like PWM or PDM to encode data into light pulses. ➡️ Each key on your remote corresponds to a unique code ➡️That code is sent using bursts of IR light, modulated with PWM ➡️The receiver decodes the duration and gaps between pulses to figure out the command This is how your TV knows you pressed volume up, not power off. ⚙️ Why PWM? Resistant to noise Easy to implement in hardware Efficient for short-range line-of-sight communication 🤯 You thought PWM was only for motor control? Turns out — it’s literally in your hand, every time you use your remote. 💬 So next time you press a button on your remote… Remember: you’re not just flipping channels. You’re engaging a classic embedded system concept — in action! #EmbeddedSystems #microcontroller #programming #C #Cprogramming #SignalProcessing #TechFacts #Electronics

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Chip Validation is Broken—And It's Costing the Industry Billions NVIDIA ($2T market cap), Intel ($150B+), AMD ($300B) — all pushing the limits of chip design. But nobody’s talking about the hidden bottleneck slowing their progress: Validation inefficiencies that delay launches and burn resources. These aren’t isolated issues. They’re systemic failures. Before a chip hits the market, it undergoes extensive testing to ensure it performs as expected under real-world conditions. This process—chip validation—is crucial for verifying functionality, performance, and reliability. But validation today is painfully slow. Engineers spend weeks scripting and running tests manually, dealing with fragmented tools, and sifting through scattered data to debug issues. The result? Delays, inefficiencies, and skyrocketing costs. The Broken Playbook -Weeks spent scripting tests instead of analyzing results -Scattered data across tools, slowing debugging cycles -Manual processes introducing errors and inefficiencies Behind the cutting-edge innovation lies a brutal truth: Validation is stuck in the past the last software that was built for validation released in 2001 (LabView). The Future of Validation: A new era is emerging: Automated, AI-driven validation workflows. And the results are game-changing: 20x faster test execution Fewer errors, more actionable insights Seamless collaboration across teams At Atoms, we’re not just talking about the future—we’re building it: One platform to automate and accelerate chip validation AI-assisted workflows to streamline debugging Real-time insights for faster decision-making Because while traditional validation burns months, the companies of the future are already moving at light speed. The old methods had their time. The age of AI-powered validation has begun. #Semiconductors #ChipValidation #FasterTimeToMarket #TestFlow

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