Arjun Aravind

The team implemented two different Automatic Test Pattern Generators (based on D-algorithm and PODEM), two different fault simulators (parallel and deductive), and a pre-processor.

 Phase 1: Wrote assembly codes for a parallel program to run on different threads on a core using lock and lockless mechanisms to maintain sequential consistency and coherency
 Phase 2: Implemented certain design aspects of the processor core such as thread scheduler, WB-after stage, forwarding to ID/TS and ran the parallel program on the CMP synthesized on the Spartan-6 FPGA

 Implemented a single clocked FIFO design using N and N+1 bit pointers and used it to develop an even-odd sequence arrangement
 Dual clock FIFO design with double synchronization to reduce MTBF and eliminate clock domain crossing
 Synchronized gray-coded pointers and tapped data from appropriate points to suit SSRAM design

 Phase 1: Described the Branch Prediction Buffer, Issue unit, Free-Register List corresponding to the Physical Register file, Store Buffers and Store Address Buffers for the out-of-order executing Tomasulo Processor in VHDL
 Phase 2: Wrote the RTL (in VHDL) for the Dispatch unit, Re-Order Buffer and Copy-Free Checkpoint mechanism with Dirty Bit Arrays to model FRATs and flush wrong path instructions in case of branch mis-prediction
 Phase 3: Synthesized the out-of-order executing… Show more

 Phase 1: Described the Branch Prediction Buffer, Issue unit, Free-Register List corresponding to the Physical Register file, Store Buffers and Store Address Buffers for the out-of-order executing Tomasulo Processor in VHDL
 Phase 2: Wrote the RTL (in VHDL) for the Dispatch unit, Re-Order Buffer and Copy-Free Checkpoint mechanism with Dirty Bit Arrays to model FRATs and flush wrong path instructions in case of branch mis-prediction
 Phase 3: Synthesized the out-of-order executing Tomasulo processor on the Artix-7 FPGA using XST on Xilinx ISE, real time debug using Chipscope and verified the working of the dumped processor for different instruction streams Show less

A 5 stage linear pipelined MIPS CPU design was designed that tackled control, data and name dependencies. Synchronous SRAMs were used to instantiate the Instruction Memory and Data Memories (BRAM instantiations by Xilinx) and therefore, the design seemed to convert the 5-stage pipeline to an inefficient 7-stage (for flow-through BRAMs) and 9-stage (for pipelined BRAMs) pipeline. However, using the concept of shadow and keep registers, the design was converted back to an efficient 5-stage… Show more

A 5 stage linear pipelined MIPS CPU design was designed that tackled control, data and name dependencies. Synchronous SRAMs were used to instantiate the Instruction Memory and Data Memories (BRAM instantiations by Xilinx) and therefore, the design seemed to convert the 5-stage pipeline to an inefficient 7-stage (for flow-through BRAMs) and 9-stage (for pipelined BRAMs) pipeline. However, using the concept of shadow and keep registers, the design was converted back to an efficient 5-stage pipeline that modeled the modifications made by the BRAM. Show less

 Interfaced processor tiles with memory using an AXI interconnect with deterministic routing in a mesh network

 Created a master and slave interface between router and processor/ memory to generate/ receive/ reorder packets

 Requests from different processors completed out-of-order and requests from same processor completed in-order

In this project, an existing out-of-order super-scalar processor simulator, SimpleScalar, reads a machine configuration file and generates a processor model that matches the requirements specified in the configuration file. The configuration file specifies parameters such as the size and associativity of caches, number of Reservation Stations, number of functional units etc. In the SimpleScalar simulator, the functionality of Reservation Station and ROB are merged into a single entity called… Show more

In this project, an existing out-of-order super-scalar processor simulator, SimpleScalar, reads a machine configuration file and generates a processor model that matches the requirements specified in the configuration file. The configuration file specifies parameters such as the size and associativity of caches, number of Reservation Stations, number of functional units etc. In the SimpleScalar simulator, the functionality of Reservation Station and ROB are merged into a single entity called Register Update Unit (RUU).

Cacti is a tool that estimates the access time and power consumption of any structure that stores data, such as the RUU and cache structure. The input to Cacti is the size of the structure, cache associativity and process technology used in building the structure. Cacti is used to compute the latency of the RUU and caches. Finally, a simple area estimation tool is used that is provided as an Excel spreadsheet.

Two benchmark programs are used from the SPEC CPU2000 benchmark - gcc for integer benchmarks and mesa for floating point benchmarks. Show less

The goal was to generate a layout and verify the 4-core Multi-threaded Tiled "Gold" Chip Multiprocessor (CMP) using some of the CAD tools typically used in ASIC Design for performing netlist synthesis, static timing analysis, gate-level simulation, logical equivalence checking, place & route, and back-annotated simulation - namely, Design Compiler, PrimeTime, Conformal and Velocity (Encounter). Most of the time was spent on simply obtaining a synthesizable design and optimizing the area-delay… Show more

The goal was to generate a layout and verify the 4-core Multi-threaded Tiled "Gold" Chip Multiprocessor (CMP) using some of the CAD tools typically used in ASIC Design for performing netlist synthesis, static timing analysis, gate-level simulation, logical equivalence checking, place & route, and back-annotated simulation - namely, Design Compiler, PrimeTime, Conformal and Velocity (Encounter). Most of the time was spent on simply obtaining a synthesizable design and optimizing the area-delay product of the synthesized design. The synthesized netlist targets the NCSU 45nm standard cell library.

We described the Hardware for the following parts of the CMP using Verilog -

- "Gold" Network on Chip Bidirectional Ring Router with ability to avoid packet collision using virtual channels on even-odd clock polarity and round robin priorities

- "Gold" variable width Microprocessor with ability to counter data, control, structural and name dependencies for a custom made "Gold" ISA

- "Gold" Network Interface Component to enable interactions between the microprocessor and the Router for thread switching applications

- "Gold" CMP - The integration of all the above components in a structural and hierarchical manner Show less

Building up libraries for static taken and not taken branch predictors as well as dynamic bimodal and two level predictors using C++ and comparing their behavior using performance evaluation metrics such as prediction rates.

- Implemented a 5-Stage Design with Instruction Fetch (IF), Instruction Decode (ID), Execution stage 1 (EX1), Execution stage 2 (EX2), and Write Back Stage (WB) stages to execute basic arithmetic functions
- More custom functions were implemented showcasing the basic concepts of pipelining such as data-stationary control, forwarding and stalling
- Data dependencies were taken care of by designing an appropriate forwarding unit (FU) and a hazard detection unit (HDU)

A general purpose Multi-Cycle CPU can support simple Instructions such as Add, Subtract, Bitwise operations, Store Word, and Load Word. A simple structure of a CPU contains Decoding Logic, Register File, Execution Units, Memory, and other surrounding circuitry. The design included a 32-bit ALU with dynamic operation, a 1024-bit SRAM to load and store data from the memory and 8 32-bit registers as part of the register file.

In this project, we try to implement a simple general purpose… Show more

A general purpose Multi-Cycle CPU can support simple Instructions such as Add, Subtract, Bitwise operations, Store Word, and Load Word. A simple structure of a CPU contains Decoding Logic, Register File, Execution Units, Memory, and other surrounding circuitry. The design included a 32-bit ALU with dynamic operation, a 1024-bit SRAM to load and store data from the memory and 8 32-bit registers as part of the register file.

In this project, we try to implement a simple general purpose CPU with the knowledge that we gained in the course EE577A, which included adders, multipliers and SRAMs. Aided by scripting in Perl for the EE577A labs, we aim at optimizing the area, delay, and power.

Note that the CPU designed in this final project may not be exactly the same as the ones we learnt in our computer architecture courses. One main component of our course EE577A is optimization for delay and power, and therefore in addition to functionality correctness, we were supposed to implement at least one of the circuit blocks using dynamic logic. Also we need to take at least one power optimization measure learnt and we used clock gating. For delay optimization, we used minimization of critical path delay using logical effort. Show less

Major project as part of course curriculum - The major project tries to replicate, recreate and prototype "The Machine" from the hit network TV series "Person of Interest" which initially looks at teaching a central arbiter, the classification of real time videos and prediction of occurrence of cataclysmic events based on the model we develop. For now, a prototype on prediction of criminal/ suspicious activities ranging from petty thefts to hazardous terror attacks in public surveillance… Show more

Major project as part of course curriculum - The major project tries to replicate, recreate and prototype "The Machine" from the hit network TV series "Person of Interest" which initially looks at teaching a central arbiter, the classification of real time videos and prediction of occurrence of cataclysmic events based on the model we develop. For now, a prototype on prediction of criminal/ suspicious activities ranging from petty thefts to hazardous terror attacks in public surveillance systems has been abstracted. Show less

The goal of this project is to develop on an FPGA, a high-speed algorithm to track shapes (mainly circle based) and calculate their barycentres. Based on an existing camera working with infra-red light at 1280x1024 pixels and 150 frames per second, the embedded FPGA acquires the image and find some shapes. This camera is then used for motion tracking and sends through USB, the coordinates of the detected shapes. The algorithm works with low latency and tracks a moving point. It well… Show more

The goal of this project is to develop on an FPGA, a high-speed algorithm to track shapes (mainly circle based) and calculate their barycentres. Based on an existing camera working with infra-red light at 1280x1024 pixels and 150 frames per second, the embedded FPGA acquires the image and find some shapes. This camera is then used for motion tracking and sends through USB, the coordinates of the detected shapes. The algorithm works with low latency and tracks a moving point. It well differentiates small dots from bigger shapes and detects blinking points. It calculates the blinking frequency of each dot. Algorithms are developed in VHDL, simulated and tested in real condition using the camera and the JTAG debugging interface. Each data extraction is done in less than one frame.

A current working camera with an FPGA exists. A black and white image is stored into the embedded RAM of the FPGA. The communication with the USB is already implemented with a Qt visual application allowing to capture grey level images and get computed data.

Technologies/ Methodologies used:

* CMOS based Camera design using an FPGA
* FPGA - Xilinx Spartan-6
* USB
* Embedded Tracking Algorithms
* Shape Recognition
* Blob Detection and Labeling Analyses
* Shape Barycenter Calculation
* Qt visual application development Show less

A multiplier unit based on the 7-bit encoding scheme for mixed radix number systems and subsequent implementation on an FPGA

Completed during the internship at HES-SO, Geneva with Johnathan Dustour

#Prototyped and Manufactured an Infra-Red Camera for converting any surface into a touchscreen

# VHDL modelling of Data acquisition modules, Clock Management Module, Serializer-Deserializer Module, Image Treatment Module and USB Arbiter Module

Development of a glue-logic for a MetaCORE to enable faster communication between two or more parallel OpenRISC processors in HDL

Digital Signal Processing Mini-Project as part of the Course Curriculum

Simulation and Processing on MATLAB

VLSI-Design based mini-project as part of the Course Curriculum

Layout for the unit was done using the VLSI-CAD, MAGIC tool for Ubuntu
Circuit level and Logic level simulations on ngSPICE and IrSIM

Performance Parameters considered: Switching power consumed, Area occupied, Dynamic power loss, Overall size of die for implementation

Conclusion: NAND based ROM provided better results

A team based embedded systems project dealing with the navigation of a robot to a destination set by the master who communicates with the bot using GSM network while the bot also avoids obstacles in the process; once it reaches the final destination, it captures images using a Raspberry PI, enabling us to have a 360 degree view of the surroundings with respect to the azimuthal plane. The image captured is immediately fed to the master who surveys the location through a Dropbox account for which… Show more

A team based embedded systems project dealing with the navigation of a robot to a destination set by the master who communicates with the bot using GSM network while the bot also avoids obstacles in the process; once it reaches the final destination, it captures images using a Raspberry PI, enabling us to have a 360 degree view of the surroundings with respect to the azimuthal plane. The image captured is immediately fed to the master who surveys the location through a Dropbox account for which an API was developed.

Funding from the Department of Electronics and Communication Engineering, NITK and IEEE-NITK Chapter Show less

A team venture to design a low cost and competent solution to tackle environmental issues like global warming and increasing pollution levels for further climate processing applications, taken up as a project under the Institution of Electrical and Electronics Engineers Consortium, NITK Chapter

Wireless water flow monitoring and actuating solution for wide geographical surveys - A team venture to design a competent solution for assessment of water resources for the Texas Instruments Innovation Challenge - 2013/14

Development of serial communication protocols between a Virtex-5 FXT FPGA containing the PowerPC440 Processor and multiple ADuC-841 microcontroller boards using the PCI-Express and the Aurora protocol