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Specialties: CPU and SoC architecture, microarchitecture, design and verification;…
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Bondan Rufen posted thisSynopsys + OpenAI made me wonder: What happens to agentic chip-design startups that don’t own any EDA tools? The Big 3 already own the simulators, synthesis, P&R, signoff, and verification stack. Now they can put frontier AI directly on top of it. Interestingly, Xezim has gotten limited traction from agentic EDA startups — while large fabless companies are actively exploring it. Maybe the real opportunity is not another agent on top of existing tools. Maybe it’s building the tools that agents will actually use.
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Bondan Rufen shared thisI've been spending a lot of time looking under the hood of SystemVerilog simulation. Two choices have a huge impact on both correctness and performance: 4-state vs. 2-state 0/1/X/Z gives us the semantics needed for real verification, but it comes with a cost. When values are known to be only 0/1, execution can be much closer to native CPU operations. Event-driven vs. cycle-based SystemVerilog is fundamentally event-driven. But a lot of synchronous RTL is predictable enough that parts of the execution can potentially be statically scheduled instead of repeatedly going through the event queue. The interesting question isn't really: "Event-driven or cycle-based?" It's: How much dynamic work can we turn into static execution without changing SystemVerilog behavior? I put together a short tutorial covering: - 4-state vs. 2-state simulation - X/Z propagation - event-driven scheduling - cycle-based execution - why pure cycle simulation doesn't work for full SV - hybrid execution and static scheduling
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Bondan Rufen reposted thisBondan Rufen reposted thisWant to try out xezim, but don't want to build from source? EDAPack just added multi-platform binary builds of the xezim that you can download, unpack, and use. https://lnkd.in/d75TNAvJ
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Bondan Rufen posted thisMany say AI is not ready for autopilot coding. But I’m excited to see Xezim, a Rust-based SystemVerilog simulator built almost entirely with AI coding, now actively used by engineers at companies worth more than $1T. It started small. One feature at a time. Bottom-up. Debug, iterate, improve — until it became a fully functional simulator that engineers can use on real projects. This is probably the most interesting part of AI coding to me: not generating a demo, but building a complex engineering system over time. Big shout-out to everyone who has contributed, tried Xezim, reported bugs, and shared feedback. Still a long way to go, but the progress is encouraging.
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Bondan Rufen shared thisxezim 0.11.0 is out — the open-source SystemVerilog simulator written in Rust. This release focused on closing the gap with commercial simulators, with behaviour checked against a commercial reference simulator: • Code coverage: statement, branch and toggle coverage (--code-coverage), plus much more complete functional coverage: covergroups in modules, interfaces and packages, cross selects, transition bins and cover sequence. • Constrained random: joint solving of sum(), unique and ordering constraints, dist weights, solve…before, and inline constraints that bind to the caller's scope. • UVM: built-in UVM DPI (regex, backdoor access, command line) and dozens of conformance fixes. On our UVM stress bench it now needs less than half the host instructions per transaction, and about a third fewer on the axi4 VIP. • Timing checks with notifiers, and SDF timing-check annotation. • Easier to adopt: quiet transcripts, file:line:col diagnostics, and command lines written for other simulators run as-is. • Conformance: 99.0% of the sv-tests suite passes, up from 94.0%, and more than 400 new regression tests. Claude Opus 5.5 did a great job closing gaps and fixing bugs, running several agents in parallel. Release notes: https://lnkd.in/gpwThjar Repo: https://lnkd.in/gnvkvRg7
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Bondan Rufen posted thisIt’s encouraging to start getting feedback from engineers at different companies who are using xezim in their actual projects. For an open-source SystemVerilog simulator, real-world usage is where the most valuable feedback comes from different RTL styles, testbenches, workloads, corner cases, and performance expectations that are difficult to reproduce with internal testing alone. Every issue report and suggestion helps make xezim better. I’m looking forward to hearing from more users as adoption grows. If you’re trying xezim on your project, I’d really appreciate your feedback, good or bad. That’s how the tool improves.
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Bondan Rufen shared this“Low power” has become one of the most abused terms in AI accelerators. 600W? 700W? Less than 1kW? Apparently everything is low power now. That’s why I find the Qualcomm + AWS AI inference collaboration interesting. I worked on Qualcomm’s 2nd-generation AI inference accelerator, and later around Nuvia CPU integration into Qualcomm SoCs. One thing Qualcomm understands extremely well: performance under a power constraint. Combine that with the ex-Nuvia CPU team, AI accelerator experience, and AWS infrastructure knowledge, and I would take this effort seriously. But I think the bigger issue for the flood of AI inference accelerator startups is not hardware. It’s software. Everyone can show TOPS/W charts. The harder questions are: Can developers easily use it? Can existing models move over without major effort? Does the performance survive real workloads? What happens to efficiency after CPU, memory, networking, cooling, and utilization are included? A great chip with a painful software stack is still a difficult product. NVIDIA understood this a long time ago. CUDA may be a bigger moat than the GPU itself. My prediction for this wave of AI inference accelerators: We will see many impressive chips. Far fewer successful ecosystems.AI Inference Has a “Low Power” Marketing Problem — Why I Take Qualcomm + AWS SeriouslyAI Inference Has a “Low Power” Marketing Problem — Why I Take Qualcomm + AWS Seriously
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Bondan Rufen shared thisJust found out that Fable 5.1 xhigh can self-debug and even generate its own bug reports.
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Bondan Rufen shared thisThe news that SemiAnalysis acquired Citrini Research made me think back to when I first met Dylan Patel in 2022, when he was still essentially a solo analyst. I also had the chance to help him compile a RISC-V market report. What he has built since then is impressive. To me, Dylan’s real strength is not just understanding complex semiconductor technology, but translating it into plain language that investors and executives can actually use. That helped SemiAnalysis fill a real gap between deep technical knowledge and market analysis. It is also a great example of how a younger generation can break into an industry traditionally dominated by decades of experience—not by knowing more than every veteran, but by seeing a gap the established industry overlooked. Congratulations to Dylan and the SemiAnalysis team.What SemiAnalysis Got Right About Market IntelligenceWhat SemiAnalysis Got Right About Market Intelligence
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Bondan Rufen liked thisBondan Rufen liked thisI simulated this 234 V power stage (snubbers, parasitics, three switches) for 5 ms in pure SystemVerilog. No analog solver, no AMS license. Runtime: 0.9 seconds. The picture below represents a power converter architecture described by G. Lefevre and S. Mollov 'A Soft-Switched Asymmetric Flying Capacitor Boost Converter with Synchronous Rectification'. This converter 'just works'. There's no ADC/DACs, no advanced digital control loops, and it still works well. What I learned from my recent work on another power converter (with 3 control loops), is that we can push for much better efficiency with a little bit of digital sauce on top, and what if not SystemVerilog is better suited for the job? Ok, I admit, the converter below is not going to be implemented on-chip, but the methodology still applies. SystemVerilog is the right tool for the job, and can get you from zero to the fully simulated circuit like below in no time. #DMS #SystemVerilog #PowerConverter #MixedSignal #Verification
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Bondan Rufen liked thisBondan Rufen liked thisEvery video pipeline needs a known good source before it can go out to the field ... 📺 I will not be using vendor TPG IP anymore and I'm happy to share vtpgZero (Video Test Pattern Generator) is an open-source video test pattern generator: *8 patterns (run time and build time selectable) *RGB / RAW-Bayer (like an image sensor!) / YUV *8–16 bits per component *1–8 pixels per clock. *AXI4-Stream out, AXI4-Lite config, optional FVAL/LVAL/DVAL adapter vtpgZero generates SMPTE colour bars, horizontal gradient, vertical gradient, checkerboard, solid colour, crosshatch/grid, colour ramp and LFSR noise. Plus an animated bouncing box that overlays any of them, with runtime-configurable colour, size, speed and border. Moving pixels prove a pipeline is live in a way a still frame never can. ~546 LUTs at its smallest. License: Apache-2.0. Check it out: https://lnkd.in/gr5DJgk4 #FPGA #Video #AXI #OpenSource #HDMI #SDI #MIPI #HardwareDesign
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Bondan Rufen liked thisBondan Rufen liked thisChip Industry Technical Paper Roundup: New technical papers recently added to Semiconductor Engineering’s library https://lnkd.in/g2bB63tM #semiconductor #BEOL #interconnects #DRC #chiplets #3DIC #LLMs #EDA #neuromorphic Purdue University Anushka Mukherjee, Kang He Kaushik Roy New York University Afsara Khan Austin Rovinski Peking University Zifeng Huang, Tianyu Jia, Runsheng Wang University of Michigan Haoran Jin, Zhiheng Zhang, Barry Lyu, Kangqi Zhang University of Technology Sydney, ShanghaiTech University, Technical University of Munich Kuiye Ding, The University of Edinburgh Cristian Sestito, Themis Prodromakis Heidelberg University Johannes Schemmel
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Bondan Rufen liked thisBondan Rufen liked this👋 Meet GPT-Synopsys. GPT-Synopsys brings together OpenAI frontier models with Synopsys Incs EDA technology and domain expertise. This enables the specialized model to reason about chip design and verification, and to directly operate Synopsys tools. Learn more about todays announcement: bit.ly/46Y1SBl
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Bondan Rufen liked thisBondan Rufen liked thisThe tech winter cooled down a lot of founder ambition in Indonesia. Funding got tight, and many good builders went back to corporate jobs. However, I believe this is actually the best time to build. With AI, a team of 2–3 people can now validate an idea, ship a working product, and find first customers in weeks, not years. The barrier is no longer capital or a big engineering team, it's the willingness to start and to solve a real problem. This session from Founder Institute, "How to Launch an AI Company in 2026", is a good primer for anyone sitting on an idea: https://lnkd.in/gFFM8Hdu. If you're an Indonesian builder thinking about going AI-native, let's talk.How to Launch an AI Company in 2026 w/ Connor SattelyHow to Launch an AI Company in 2026 w/ Connor Sattely
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Bondan Rufen liked thisBondan Rufen liked thisDVClub Dallas - September 22, 2026, Presenter, Cliff CummingsDVClub Dallas - September 22, 2026, Presenter, Cliff Cummings
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Bondan Rufen liked thisBondan Rufen liked thisAI is changing what our customers engineer and how they engineer it. Silicon and systems design teams are facing compounding complexity, accelerating pace and increasing cost. And there is no margin for error. First-time-right is a must. It's why we are re-engineering engineering. At Synopsys Investor Day, we detailed our long-term growth strategy and how we are engaging with customers and partners in new, differentiated ways. We announced a multi-year partnership with OpenAI to develop and deliver GPT-Synopsys, a specialized model for chip design. And earlier this week, we introduced a broad portfolio of AgentEngineer solutions and our new Autopilot Platform for autonomous engineering. We're also expanding our silicon IP business to support the growing demand for custom silicon and application-optimized IP (AOIP). Today we announced a multi-year, $1B+ agreement with Amazon to deliver AOIP that helps accelerate the development of Amazon custom chips. The expansion of digital and physical AI and the AI-driven transformation of engineering will rely on world-class IP and ground-truth EDA and simulation engines, developed and refined over decades and grounded in physics. Our customers tell us: "In AI we believe, but in physics we trust." Our leading portfolio of engineering solutions is mission critical for the future of silicon-to-systems design, and our growth is accelerating as a result. More here: bit.ly/3Vh7owo
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Marvell Technology
Scaling AI with data-centric computing at OCP 2025. The track Data Centric Computing Workshop at the Open Compute Project Foundation Global Summit will explore hardware and software innovations that bring compute closer to data for the AI era. Marvell engineers will share perspectives on how open frameworks and near memory acceleration are enabling efficient AI performance at scale: 🔹 OpenXLA: Portable Performance for the Heterogeneous Hardware Era Speakers: Gaurav Agarwal, senior director engineering, and Srihari Karnam, senior principal engineer 🔹 Efficient AI Serving at Scale: Processing Near Memory Acceleration for LLMs and Vector Search Speakers: Gaurav Agarwal, Howard Borchew, distinguished engineer, and Jayjeet Chakraborty, analyst intern, AI Solutions See the full OCP lineup here: https://mrvl.co/4n5KvVN
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Amit Tanwar
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