Leonardo Capossio

OPTIMUM SIGNAL PROCESSING DSP Very large order (p > 512–1024) → fast matrix solvers (Cholesky with pivoting, QR, SVD) or approximate methods are preferred Deep learning front-ends → neural networks or transformer-based predictors often outperform classical methods Massive MIMO / STAP in large arrays → Krylov subspace methods, randomized SVD, or GPU-accelerated full solvers https://lnkd.in/ehbywVbX

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I recently attended interviews with AST SpaceMobile and Astra Microwave Products Limited, and I wanted to share some of the questions I was asked. This might help others preparing for VLSI / Verification / RTL interviews. AST SpaceMobile Tell me about yourself. Write a constraint to generate addresses that are multiples of 4. Also, write an assertion to ensure that when req is high, gnt becomes high within 2 cycles. Draw the timing diagram for the APB Protocol. How do you start a UVM sequencer? What is the difference between an active agent and a passive agent? Explain your project and how you implemented it. Astra Microwave Products Limited Draw an AND gate using only NOR gates. What is the difference between functions and tasks in Verilog/SystemVerilog? How does a MUX compare with a decoder or encoder? How would you rate yourself in C, Verilog, and SystemVerilog? What is the difference between combinational and sequential circuits? These questions covered a good mix of digital fundamentals, Verilog/SystemVerilog, UVM, assertions, constraints, and protocol knowledge. For anyone preparing for VLSI interviews, I hope this helps. 🚀 #VLSI #Verification #SystemVerilog #Verilog #UVM #RTL #APB #DigitalDesign #Semiconductor #InterviewPreparation #VLSIJobs

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🧑‍🚀GPT-Astra killed Altium Designer. Usually, all “real” engineers make long nose at KiCad because of the Hobbyist Too amateur High speed Whatever reason. Since GPT-Astra 6 nothing. No laughing. No trash talks. Where the h3ll are Altium® Designer fans and advocates? If you want to read all of my posts, use the #thatkicadguy tag in the search field above

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74 Comments

Ever wondered what actually goes into an ASIC/FPGA Physical Design flow? 🔌🕵️‍♂️ Physical Design isn't just about "drawing wires"—it’s about managing a complex ecosystem of data files! 🌐 Each file type serves as a critical blueprint for the final chip. 🏗️💎 Here is a quick breakdown of the "Big 9" inputs that make the magic happen: 🪄👇 1. Netlist (.v): The logical "skeleton" of your design! 🦴💻 2. SDC: The official rulebook for Timing and Clock constraints! ⏱️📏 3. Physical Library (.lef): The "Lego blocks" – dimensions and pin positions! 🧱📍 4. Logical Library (.lib/.db): The brain! Timing, Power, and Functionality at different PVTs! 🧠⚡ 5. Technology File (.tf): The manufacturer’s law – Metal layers, Vias, and DRC! 🏗️📜 6. TLU+ / RC Files: Essential for accurate post-route delay calculations! 🔍📉 7. UPF/CPF (Power Intent): Defining power domains for those ultra-low-power designs! 🔋🔌 8. DEF: The bridge for placement and routing info! 🌉🗺️ 9. Scan DEF (DFT): Ensuring the chip is testable and reliable! 🧪✅ The Ultimate Goal? 🏁 Turning all these inputs into a perfect GDSII—the final layout ready for the foundry to bake! 🥧🏭 #PhysicalDesign #ASIC #FPGA #Semiconductors #VLSI #Engineering #ChipDesign #TechExplained #HardwareEngineering #Silicon #DigitalDesign #ElectronicEngineering #Innovation #TechCommunity #STEM #GDSII #Netlist #TimingClosure #RTLtoGDSII #IntegratedCircuits #Microchips #SemiconductorIndustry #EngineeringLife #CareerInTech

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