Balaji Gudavalli

*** Why Silicons (Chips) Fail in System Bring-Up? *** Imagine silicon comes back from the fab. Everyone’s excited. Power it up, Run the first tests… and Critical basic function don’t work. This moment separates experienced teams from the rest. Because at this stage, it’s never just a Design issue—it’s an Interaction issue: o Analog, Digital, Verification, Firmware, and Test Teams, all meeting for the first time in real hardware. o Validation engineers uncovering behaviors no simulation ever caught. o Debugging across five different domains at once. You can’t simulate everything. But you can "prepare." The best teams don’t just verify IPs—they build a "Bring-up Mindset" into the entire development process. What’s the trickiest bring-up issue you’ve ever faced?

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RF Basics: Down-Conversion Mixer A down-conversion mixer is a crucial component in radio frequency (RF) systems, especially in receivers. Its primary function is to lower the frequency of an incoming RF signal to an intermediate frequency (IF) or baseband frequency, making it easier to process and amplify. Here's how a down-conversion mixer works and why it's important: 1. The mixing process: A down-conversion mixer has three ports: an RF input, a local oscillator (LO) input, and an IF output. The RF port receives the high-frequency signal that needs to be down-converted. The LO port receives a steady, high-frequency signal generated by a local oscillator. The mixer combines these two signals using a nonlinear element (like diodes or transistors). This mixing process creates new frequencies at the output, including the sum (RF + LO) and difference (RF - LO) of the input frequencies. 2. Down-conversion to IF: In a down-conversion mixer, the desired output is the difference frequency (f_RF - f_LO) which is at a lower frequency than the input RF signal. This lower frequency is known as the intermediate frequency (IF). This process allows for better filtering of unwanted signals and noise at the lower frequency range, ultimately improving the signal-to-noise ratio. 3. Applications: Down-conversion mixers are widely used in receivers, particularly in superheterodyne receivers, which are common in radios, televisions, and cellular base stations. They are also essential in radar systems, satellite communications, and other applications requiring frequency translation for signal processing. 4. Importance in RF systems: Efficient signal handling: Down-conversion enables systems to process high-frequency signals more effectively by shifting them to a more manageable frequency band. Improved selectivity and sensitivity: Filtering is more effective at lower frequencies, allowing the receiver to better isolate the desired signal from interference and noise. Enhanced system performance: By reducing the frequency and facilitating filtering, down-conversion mixers contribute to overall system performance and efficiency. In essence, down-conversion mixers are key to making high-frequency signals accessible and manageable for various RF applications, contributing significantly to the performance of modern communication and electronic systems. 🙏🙏🙏🙏🙏

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The ‘world’s smallest #microcontroller’ measures just 1.38 mm² and costs 20 cents 🤯😍 - This Arm Cortex-MO+ powered MCU was showcased at embedded world Exhibition&Conference 🤩 Texas Instruments (#TI) unveiled what it claims to be “the world's smallest microcontroller (#MCU)” at Embedded World 2025. The tiny new MSPM0C1104 measures just 1.38 mm², which TI says is about the same size as a black pepper flake. TI is targeting #medical #wearables and personal #electronic applications for the new MSPM0C1104, which it claims is 38% smaller than the most compact rival MCUs and will cost buyers just 20 cents a piece in bulk. Thanks again to Mark Tyson and Tom's Hardware for the full article 🤩🙏 #semiconductorindustry #semiconductors #semiconductor #technology #tech #it #chip #chips #usa #geopolitics #ic #icdesign #texas #it #ai #iot

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Infineon Technologies to buy Marvell Technology's auto ethernet business for $2.5 billion 💡💰🤩 German chipmaker Infineon Technologies, said on Monday it would buy Marvell Technology's #automotive #ethernet business for about $2.5 billion in cash, to expand its #microcontroller segment. The automotive ethernet business, which will become a part of #Infineon's #automotive division, is expected to generate revenue between $225 million and $250 million in calendar year 2025, with a gross margin of nearly 60%. Infineon has secured acquisition financing from banks, will incur additional debt to finance the deal, and expects it to close this year. "#Marvell has made it abundantly clear that they are an #AI- first company, focusing on both custom #silicon and #networking," said CJ Muse, senior managing director, Cantor Fitzgerald. "With that as a backdrop, it would make sense that automotive ethernet would be less of a focus and therefore something they would be willing to sell at the right price. At 10x sales, that's a fairly attractive price." A very big thank you again to Reuters for the full article with more background and insights via the link below 💡🙏👇 https://lnkd.in/eTgv5fKk #semiconductorindustry #semiconductors #semiconductor #technology #tech #it #datacener #genai #chip #chips #geopolitics #usa #germany

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NVIDIA picks Micron Technology for massive SOCAMM rollout 🤩 #Nvidia is preparing to enter a new phase in the memory market by planning to deploy between 600,000 and 800,000 SOCAMM modules in 2025. This initiative positions SOCAMM as a potential successor to high-bandwidth memory (#HBM). Although the initial deployment volumes are relatively modest compared to HBM, industry analysts suggest the move could trigger a wider transformation in the #memory and substrate sectors. According to reports from ET News and Wccftech, Nvidia has confirmed its intent to integrate SOCAMM into its next-generation #AI products, sharing projected order quantities with key #memory and substrate suppliers. The company's upcoming GB300 "Blackwell" platform will be among the first to adopt SOCAMM, alongside the AI PC Digits, unveiled during Nvidia's GTC 2025 conference in May. Nvidia initially tapped Samsung Electronics, SK hynix, and Micron Technology to co-develop SOCAMM. However, #Micron has emerged as the first memory maker to receive approval for volume production, outpacing its South Korean rivals in the race to support Nvidia's latest architectures. Thanks again to Amy Fan , Sherri Wang and DIGITIMES Asia for the full article with more background and insights via the link below 💡🙏👇 https://lnkd.in/eAjnXYQu #semiconductorindustry #semiconductors #technology #tech #innovation #usa #taiwan #geopolitics #datecenter #dram #ai #server #chip #ic #aiot

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Texas Instruments Faces Prolonged Market Headwinds Amid Tariff and Demand Uncertainty Shares of Texas Instruments (TI) fell 6% on Wednesday following a downbeat fourth-quarter forecast, signaling extended weakness in the analog chip market. The company expects Q4 revenue of $4.4 billion and earnings per share of $1.26, both below analyst estimates. Despite TI’s $60 billion investment in expanding U.S. manufacturing, the rebound in analog demand remains subdued. Analysts cite an uncertain global economy, cautious industrial spending, and unresolved U.S.–China tariff rules as key headwinds. Brokerages including Jefferies and Charter Equity Research warn softness could persist across the analog sector, with 16 firms lowering TI’s price targets. If losses hold, TI stands to lose about $10 billion in market value. Competitors ON Semiconductor, NXP Semiconductors, and Analog Devices also saw shares drop 2–3%, reflecting broader investor concerns over prolonged inventory and margin pressures. How might the evolving tariff landscape and industrial spending trends shape analog chip recovery in 2025? Thanks to Reuters for providing the full article with additional background, charts, and insights at the link below. 👇 https://lnkd.in/gYjKmUdZ #ChipDesign,#SemiconductorManufacturing, #VLSI, #Lithography, #ICPackaging

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End-to-End EDA Flow on Arm-based Compute Platforms Cadence has expanded its collaboration with Arm to deliver a complete end-to-end EDA flow optimized for Arm-based compute platforms. Our full suite of digital design, implementation, and verification tools now runs natively on Arm compute, helping you accelerate time to market and achieve first-pass silicon success. This collaboration gives chip designers greater infrastructure flexibility, scalability, and energy efficiency. Now you can tackle the most complex SoCs for AI, 5G, and hyperscale data center applications with more compute platform flexibility. “Our strategic alignment with Cadence delivers unprecedented opportunities for chip designers to leverage the combined power of Cadence’s industry-leading tools and performance-optimized processors from Arm” said Dermot O'Driscoll, SVP of Infrastructure Engineering at Arm. “This collaboration enables our customers to design, verify, and implement the most complex SoCs with greater efficiency and performance.” Discover how we're enabling the next generation of chip design. Read the blog: https://ow.ly/q24l30sRLBt #ChipDesign #EDA #Semiconductors #AI #CloudComputing

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Equalization in PCIe receivers is a set of techniques used to compensate for signal distortion (mainly inter-symbol interference, ISI) that occurs when high-speed signals travel across lossy PCB traces, connectors, and cables. At PCIe Gen3 and beyond (8 GT/s, 16 GT/s, 32 GT/s), the channel is no longer “transparent,” so the receiver must actively equalize the incoming waveform to recover clean data. ⸻ Equalization Techniques in PCIe Receiver There are three major types of equalization blocks used: 1. Continuous-Time Linear Equalizer (CTLE) • Analog filter placed in the front-end of the receiver. • Provides high-frequency boost and low-frequency attenuation to counteract channel losses (which attenuate high frequencies more). • It is a linear equalizer, so it amplifies both signal and noise at high frequency. • Adjustable CTLE settings allow adaptation depending on the channel characteristics. 2. Decision Feedback Equalizer (DFE) • Nonlinear equalizer applied after the slicer (comparator). • Works by using previously detected bits to cancel ISI in the current bit. • Very effective for channels with long tail ISI. • Advantage: does not amplify noise (unlike CTLE). • Limitation: can suffer from error propagation if a wrong decision feeds back. 3. Feed-Forward Equalizer (FFE) in TX (but coordinated with RX) • Strictly speaking, this is transmitter-side, but part of the PCIe equalization training process. • The transmitter shapes its output waveform using pre-cursor and post-cursor taps (3-tap FFE in PCIe Gen3/Gen4). • The RX participates in equalization negotiation (training sequence TS1/TS2) to request different TX FFE settings. ⸻ Equalization Process in PCIe Receiver • During link training (LTSSM, Link Training and Status State Machine), the receiver evaluates the eye opening and BER using training sequences. • It sends feedback to the transmitter (via protocol-defined messages) requesting adjustments of TX FFE taps. • At the same time, the RX adjusts its own CTLE and DFE settings to maximize eye opening. • This adaptive equalization loop ensures reliable data recovery. ⸻ Summary • CTLE → Analog, boosts high frequency to counter channel loss. • DFE → Digital, cancels post-cursor ISI using past decisions. • TX FFE → Pre/post-cursor shaping, negotiated with RX. • PCIe uses a co-optimized TX+RX equalization scheme to achieve high-speed signaling across lossy board channels.

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It's an exciting time at Texas Instruments as we announce an award agreement of up to $1.6B in direct funding through CHIPS for America, which will support three new fabs under construction in Sherman, Texas, and Lehi, Utah. https://lnkd.in/g_6bc4Tp ​

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Update - NEW SILICON PARETO CURVE, EVP: It’s been 8 months since I first posted about the concept of EVP: "I've debated this problem for a while, and many people have looked at replacing the infamous PPA Pareto curve. I have experimented with adding interconnects (including the pins) to the equation, as well as 4-letter and 5-letter replacements. After playing with several alternatives, I think EVP is probably the most effortless future transition and more straightforward to pronounce than the alternatives.” ** ENERGY, E: because our community should care not only about Performance but the "cost" of Performance, i.e., energy-in and the heat-out. Power does not accurately reflect the cost. Yes, time is a function of Performance, but it is also a function of cost. I am concerned that the industry has lost its Moral Imperative on efficiency. Reduction of logic or geometry shrinkage is a minor factor in the efficiency game and not particularly useful (2025 update, giving us 3% to 5% per shift). ** VOLUME, V: Yes, we will be moving to physical 3D silicon, no longer concerned with 2D floorplans (very 1970s). We will choose computational cubes over pancakes. We will care more about making 3D circuits cool enough to drive future computational cubes that avoid thermal nuclear meltdowns. ** PERFORMANCE, P: does not change. Performance is the metric for a satisfied consumer. Again, linked to Energy, but how much is too much? How close can we push the modern computing world towards the Margolus-Levitin limit with the available Energy without destroying the world's resources in the process?" 2025 UPDATE: That was my initial thought on replacing PPA, but there is a more fundamental consideration as well: we need to escape Euclidean geometry (2D). Yes, FinFETs and GAA transistors are 3D, but the design of logic remains 2D.  Tensors, Vectors, and Quaternions (plus alternatives) aren’t just crucial for Artificial Intelligence; they will be essential for future silicon computational design. #VaireComputing #AdiabaticReversibleComputing #PhysicsAwareComputing #NearZeroEnergyChips #Physics #Semiconductor #Future #PPA #EVP

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The cost-effective QFN package is popular in Analog ICs, but parasitics of the wirebonds can be a challenge in some applications. This is particularly true for RF ICs and DC/DC switching converters. For these applications, the FlipChip QFN package provides a logical solution. By bumping the die and flipping it onto the leadframe, FlipChip QFN combines the benefits of a standard QFN - affordability and standardization - with enhanced electrical performance and a smaller footprint. In automotive applications, FlipChip QFN also offers the option of plated-end leads, which aid in solder fillet formation, further enhancing reliability. Amkor QFN Homepage: https://bit.ly/4dAzAhS

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AI Storage Demand Accelerates HDD Replacement as NAND Flash Suppliers Shift Toward High-Capacity Nearline SSDs TrendForce Corp.’s latest investigations reveal that the surge in #AI inference applications is creating a strong need for real-time #data access and rapid processing of large data sets. As such, both #HDD and #SSD suppliers are expanding their high-capacity #storage options. Due to a notable supply shortage in the #HDD market, #NAND #Flashmemory vendors are fast-tracking their technological advancements and increasing production of ultra-high-capacity nearline SSDs. #TrendForce indicates that the HDD industry is going through a challenging shift to next-generation heat-assisted magnetic recording (HAMR). The substantial initial investment in new production lines has limited capacity growth, leading suppliers to transfer these costs to customers. As a result, the average price per GB has increased from US$0.012–0.013 to US$0.015–0.016, diminishing HDD’s main cost advantage. In contrast, #NAND Flash continues to advance through 3D stacking #technology, enabling faster capacity growth than HDD. As layer counts surpass 200 and bit density per wafer rises, 2Tb QLC chips are projected to reach mass production by 2026, significantly contributing to lower costs for nearline SSDs. #AI inference workloads involve frequent random reads of small files and quick access to model parameters. In terms of performance, #SSDs provide IOPS that are hundreds or even thousands of times greater than HDDs, with latency measured in microseconds versus the millisecond delays of HDDs. Additionally, SSDs are more power-efficient per terabyte since they lack spinning motors. Over time, large data centers can save significantly on electricity, cooling, and rack space, outweighing the higher upfront cost of SSDs. TrendForce highlights that while HDD costs might decrease once HAMR production scales up, NAND Flash has a clear structural edge in both cost decline pace and manufacturing adaptability. For NAND producers seeking growth beyond #smartphones and #PCs, the debut of the nearline #SSD market is a much-anticipated breakthrough and a key chance to challenge HDD dominance. https://lnkd.in/ejdpwYw3 Personal addition 🤓: Knowing that many HDD clients are demanding SSDs as a current replacement due to the HD shortage, the next oversupply for NAND is already called out. As soon as HDDs ramp up volume (in case they can and want to further invest in higher volumes), they will move back to the cheaper HDD and demand of NAND will fall. The NAND fabs will not be able to lower the production output in an instance...but when will this be??? 3, 6 or 9 months? And is the AI investment just a hype or will it be constantly high? #embedded #embeddedsystems #IIOT #industry40 #electronics #semiconductor #automotive #automation altec ComputerSysteme GmbH

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🚨 DFT verification is no longer just a technical hurdle—it's a strategic imperative. As silicon complexity explodes and time-to-market windows shrink, traditional simulation methods are buckling under the weight of modern ATPG and MBIST workloads. The result? Verification bottlenecks that threaten tape-out schedules and product reliability. Microsoft faced this challenge head-on: “Questa One DFT (QDX) simulation utilizes advanced DFT-centric simulation capabilities to deliver faster performance than existing simulation solutions, slashing our verification time from weeks to days,” said Selim Bilgin, corporate vice president, Silicon Engineering at Microsoft. “In addition to these impressive speed ups, on Microsoft’s Azure Cobalt 100 platform, QDX delivers up to 20 percent further performance jump unlocking even greater efficiency for our EDA workloads.” Siemens is proud to partner with industry leaders like Microsoft to redefine what’s possible in DFT verification. Questa One Sim DX—part of the broader Questa One Smart Verification solution—delivers: ✅ Serial and parallel ATPG simulation acceleration ✅ Zero-delay and timing-aware scan simulation ✅ On-the-fly reconfiguration for retargeted pattern verification ✅ MBIST/BISR simulation optimizations ✅ Multi-core and cloud-native performance scaling 🔗 Learn how Questa One Sim DX can accelerate your DFT sign-off and eliminate verification bottlenecks:👉 https://sie.ag/TeyNK #DFTVerification #EDAInnovation #QDX

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SPICE Is Now the #1 Threat to Your Schedule, Budget, and Silicon Success Your teams aren’t slow — the process is. For decades, SPICE has been the backbone of analog design. But today, it has quietly become the largest operational bottleneck inside every analog/RF organization. As a leader, you’re seeing the symptoms every day: 🔸 Projects slipping because simulations take hours or days 🔸 Teams stuck in iteration loops instead of delivering final designs 🔸 Limited ability to explore design space or understand PVT interactions 🔸 Talent stretched thin as complexity at advanced nodes explodes 🔸 Porting to new nodes taking as long as new design 🔸 SPICE runtimes blocking Monte Carlo, worst-case, and yield analysis 🔸 “Good enough” design choices made under schedule pressure 🔸 Risk of silicon failures — with analog still causing 40% of ASIC respins Even with GPU-accelerated solvers and parallelization, the fundamental problem remains: SPICE cannot keep up with the scale, speed, and complexity your programs now require. ⸻ 🔥 A Silicon-Proven Alternative for Leaders Who Need Results Analog Intelligent Design (AID) helps engineering organizations break out of the SPICE trap — without replacing SPICE. We deliver measurable outcomes engineering leaders care about: ✔️ Shorter schedules through rapid design space exploration ✔️ Higher predictability with ML models correlated 99%+ to SPICE and silicon ✔️ 1–2% variation across PVT with self-tuning analog circuits ✔️ 80–90% test-cost reduction ✔️ Faster porting to new nodes (28nm → 22FDX → 16nm → 7nm) ✔️ Higher engineering throughput without needing to hire more designers ✔️ Reduced program risk with deeper PVT and spec-interaction insight ✔️ Better first-silicon outcomes This is not theoretical. Our ML models are silicon-validated across multiple analog/RF blocks and multiple technologies. ⸻ If your mandate is: • Deliver faster • Reduce risk • Improve margins • Scale without expanding headcount • Hit schedules with confidence Then it’s time to see what’s now possible beyond traditional SPICE-driven workflows. 📩 Let’s talk. A 30-minute discussion can show you how engineering leaders are using AID to accelerate design, reduce cost, and improve first-silicon success. Contact us at Info@aianalog.co

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7 best practices for designing #RF vias 1️⃣ Design the via to maintain low return loss at the input, especially when dealing with wide bandwidths extending into the GHz range. 2️⃣ Ensure the presence of vias does not negatively impact the insertion loss. While insertion loss is not usually the focal point for vias, it is still a critical factor. 3️⃣ Maintain a minimum spacing of  λ/10 between the ground vias. For instance, at 2.4 GHz, the clearance should be 6 mm. 4️⃣ Place ground-connected vias near the PCB edges to reduce RF losses through the laminate. The EMFs are less confined near the edges. However, avoid placing them too close to the edge to prevent mechanical issues. 5️⃣ For mmWave PCBs, implement a via fence around grounded coplanar waveguides to enhance high-frequency isolation. This technique also suppresses frequencies below a cut-off and prevents mmWave interference with other signals. 6️⃣ Avoid return or stitching vias for slow-speed signals with rise times higher than 20 ns (e.g., GPIOs, I2C, and control signals) because such signals are less sensitive to impedance discontinuities. 7️⃣ Prioritize transition methods and the implementation of return paths (e.g., stitching vias) for higher-frequency signals or those with fast rise times to minimize radiation or crosstalk. 👇Check the link in the comments for more details. --> Repost for better reach. #rfengineers #radiofrequencydesigners #hardwareengieers #electricalengineering

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We are partnering with Silicon Photonics expert Lightmatter to design CPO Optical Engines (OEs) using TSMC's COUPE. 2026 is a year of OE development, 2027 will be a year of silicon validation and CPO adoption as xPU's Scale Up interface. Optical Scale Up will enable huge xPU clusters which sizes are currently limited by copper interconnet. GUC is at front edge of CPO adoption to enable xPUs with optical IOs at scale. https://lnkd.in/dHZCuHeF

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