verilator / verilator
Verilator open-source SystemVerilog simulator and lint system
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Verilator open-source SystemVerilog simulator and lint system
OpenTitan: Open source silicon root of trust
CORE-V Wally is a configurable RISC-V Processor associated with RISC-V System-on-Chip Design textbook. Contains a 5-stage pipeline, support for A, B, C, D, F, M and Q extensions, and optional caches, BP, FPU, VM/MMU, AHB, RAMs, and peripherals.
Official repository of the AWS EC2 FPGA Hardware and Software Development Kit
VeeR EL2 Core
[UNRELEASED] FP div/sqrt unit for transprecision
Simple single-port AXI memory interface
RSD: RISC-V Out-of-Order Superscalar Processor
Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.
RISC-V Debug Support for our PULP RISC-V Cores
APB Logic
Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.
Technology dependent cells instantiated in the design for generic process (simulation, FPGA)