This page and its sub pages describe the AMD Embedded Development Framework and its use to develop embedded software stacks for AMD adaptive SoC and FPGA products.

Table of Contents

Introduction to the AMD Embedded Development Framework

The AMD Embedded Development Framework (EDF) is a common framework to support platform-level development and embedded software solutions for AMD adaptive SoC and FPGA products, as well as their evaluation boards.

The framework embraces open-source development and currently includes the following: 

• Support for AMD Vivado™ Design Suite and Vitis™ software platform-based flows

• Prebuilt embedded software stacks (disk images) and pre-configured BSPs to accelerate platform exploration and product development on AMD adaptive SoC and FPGA products and their evaluation boards

  • Get evaluation boards up and running easily and quickly using prebuilt images

  • A rich Linux® Kernel and RootFS configuration - minimizing the need to re-build

  • Multi-stage boot architecture with deferred programable logic load, utilizing Segmented Configuration where available - minimizing the need to re-build and supporting on-target development

  • Supports Vitis software platform based flows via the prebuilt images

• Open-source tools for embedded software development including a Yocto Project™ based build environment

• Linux OS and RTOS based embedded software stacks 

• A common starting point for example and reference designs

• A curated and common evaluation board experience with recommended flows and configurations

Prebuilt Disk Images and Board Support Packages (BSP) - All you need to build a running system

AMD EDF disk images are created from board support packages (BSP) and are based on a common specification outlined in this documentation. The BSP contains everything needed to build a running image for a board. They can be used to re-build or extend the prebuilt images for AMD evaluation boards, or as a starting point for enabling a custom board (chip-down design).

BSPs contain:

• The hardware design - AMD Vivado Design Suite project

  • Built from a Vivado Configurable Example Design - can be extended

  • Delivered as a Tcl script and prebuilt artifacts (used by Yocto Project to re-build prebuilt disk images)

• The embedded software configuration - Yocto Project based

  • Built from a pre-defined configuration stored in the AMD Yocto Project repository - can be extended

  • Uses AMD SHEL flows Software Hardware Exchange Loop (SHEL) FlowPreview

AMD EDF Linux BSP and Prebuilt Disk Images

Open

Supports boot to AMD EDF Linux OS on the target evaluation board

• AMD Vivado Design Suite project - Downloadable as a Tcl file

• Prebuilt Vivado tool artifacts - Downloadable, and used by Yocto Project build

• EDF Linux BSP disk image and EDF Boot Firmware* – (New devices and families)

  • EDF Boot Firmware: Image selector with recovery (OSPI) and Linux utilities*

  • Arm® SystemReady compatible boot flow with UEFI

  • Rich Linux: Utilities, libraries, compilers

  • FPGA Manager / DFX Manager Linux utilities for programmable logic (PL) firmware management and load

  • AMD Vitis software platform support: Run your Vitis accelerator on the prebuilt image

  • Access to software and hardware reference designs via package feed: Download and run

  • PL payload - BSP base platform: RAM, DMA, GPIO, etc.

See the relevant sections of this document for more details on architecture and specifications.

*Evaluation boards supported for Multi-stage Boot (see table AMD Embedded Development Framework (EDF) | Device and Evaluation board support tablePreview )

Persona-Based Development Flows

AMD EDF takes a unified and open-source approach with pathways to production with relevant additional work by end users or third-party vendors, enabled by an industry-standard tools flow.

A curated evaluation board experience has been created to support rapid platform exploration and easier development paths—but with support for all device features and boot flows to support custom development.

The experience and development flows are based on common specifications and the following stages or user personas:

Open

The Development Flow pages (high-level information) and the Getting Started pages (walk-through style tutorials) are split into the personas above.

Key components and features of the framework

• Development flow support - Leveraging prebuilt images to reduce re-build cycles

  • AMD Vivado Design Suite CED-based hardware designs using a common embedded platform starting point

    • Enables Segmented Configuration based workflows - Run compatible PL designs on the live system using the prebuilt disk images.

      • AMD Technical Information Portal

      • Vivado-Design-Tutorials/Versal/Boot_and_Config/Segmented_Configuration at 2024.2 · Xilinx/Vivado-Design-Tutorials

    • Software Hardware Exchange Loop (SHEL) Flow Software Hardware Exchange Loop (SHEL) FlowPreview

  • Support for AMD Vitis software platforms

    • SDK for cross platform development

    • Run Vitis accelerators on the prebuilt live system via Segmented Configuration using the prebuilt disk images

  • Support for on-target development

    • Compilers and tool chains available

• Walk through tutorials and examples for packaging and deployment inside of Yocto Project build -
  Getting Started - Walkthrough ExamplesPreview

• Common base hardware design - Common Specifications | Embedded common platform Configurable Example Design (CED)Preview

• Processing System (PS) minimal specification - Common Specifications | PS common minimum specificationPreview

• Common boot architecture - Common Specifications | Boot Architecture for AMD Evaluation boardsPreview

  • Default - Multi-stage boot using Segmented Configuration on supported devices

Open

System memory map specification - Common Specifications | System Level Memory MapPreview

Common Linux kernel configurations and root FS - Common Specifications | EDF Linux®OSPreview

Next Steps

The following sub sections provide walk through tutorials, and more details on the flows, architecture, and specification.

We recommend starting with the Development flow pages to get an overview, and then moving to the Getting Started pages, which will walk you through booting a prebuilt image on your board.

• Development Flows - How it all worksPreview

  • Start here! - High-level introductions to the supported and recommended development flows for hardware and embedded software development.

• Getting Started - Walkthrough ExamplesPreview

  • How to get your evaluation board booted to Linux using EDF, and paths to explore further.

• https://xilinx-wiki.atlassian.net/wiki/spaces/A/pages/3250586143

  • Specification and architecture information that is applicable to all supported evaluation boards and custom development flows.

• https://xilinx-wiki.atlassian.net/wiki/spaces/A/pages/3250586239

  • Further to the common specifications, specifications that are specific to device families, series, or portfolios.

• https://xilinx-wiki.atlassian.net/wiki/spaces/A/pages/3250586284

  • Further to the device-specific specifications, evaluation board specifications including pinout, interfaces, and memory map implementation.

• https://xilinx-wiki.atlassian.net/wiki/spaces/A/pages/3250586417

  • General reference links and common acronyms.

• https://xilinx-wiki.atlassian.net/wiki/spaces/A/pages/3250586438

  • Download links, release notes, and know issues for AMD EDF releases.

Device and Evaluation Board Support Table 

All AMD adaptive SoC and FPGA products are supported by EDF.

• Packaged BSP for AMD evaluation boards. See below for current list and additional evaluation boards being added in future releases.

• All AMD adaptive SoC and FPGA products via the custom board flow: Vivado Design Suite Project (.xsa) to Yocto Project based build using EDF Linux OS.

  • https://xilinx-wiki.atlassian.net/wiki/spaces/A/pages/3250586081/Development+Flows+-+How+it+all+works#Introduction---Migrating-from-PetaLinux-%2F-Starting-from-a-Vivado-.xsa

Packaged BSP for AMD Evaluation Boards

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