Zynq UltraScale＋ MPSoC Power Management
This page provides tips and examples of power management solutions for the Zynq UltraScale+ MPSoC & RFSoC.
Table of Contents
Software Solutions
Firmware Patches
Zynq UltraScale+ MPSoC Power Advantage Tool
- Part 1 – Introduction to the Power Advantage Tool
- Part 2 – Installing the Pre-Built Power Advantage Tool
- Part 3 – Running the Pre-Built Power Advantage Tool
- Part 4 – Building and Running the SD Image
- Part 5 – Building and Running the PL Design From Sources
- Part 6 – Building and Running the R5 Design From Sources
- Part 7 – Building and Running the MSP430 Design from Sources
- Part 8 – Building and Running the Qt PC GUI Design from Sources
- Part 9 – Building and Installing the Gimp Artwork from Sources
- Part 10 – Building and Running the Linux Design From Sources
Power Management Videos
- PS: Power Management Features
- PS: Power Advantage Tool
- PS: Enabling PS Power Management
- PS: PS Power Islands
- PS: Frequency Scaling
- PS: Power Domain Switching
- PS: Driver-Based Power Management
- PL: PL Power Management Overview
- PL: PL Clock Control Types
- PL: PL Clock Control Implementation
- PL: FPGA Only Power Management Architectures
- PL: External FPGA Power Management
- PL: PL PM Design For Early Implementation and Reuse
- Adv: Schematic Design For Power Management
- Adv: DDR Power Optimization
- Adv: FSBL Power Management
- Adv: Debug Nodes
- Adv: Debug Registers
- Adv: Interconnect Clock and Standby
- Adv: Peripheral Clocks
- Adv: Saving PLLs
- Adv: Hard IP Power Management
- Adv: Applying all to VCU TRD
Product Documents
- UG1137 Zynq UltraScale+ MPSoC Software Developer Guide
- UG1200 Embedded Energy Management Interface
Related Links
Changelog
- 2018.1
- Added "Hello PM" out-of-box demo. See Linux Kernel - Out-of-box Demo.
- Enabled Wake-up on USB and LAN after suspending.
- Added support for suspend with full chip power off, and a design example. See MPSoC Power Off Suspend
- Updated Linux PM debugfs interface. See MPSoC PM - Linux Kernel
- PMU now needs to access Coresight register for FPD power down. Please see default Petalinux project for reference design (see first 5 steps of Create HDF with GPO2 polarity to High).
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