Microarchitecture Innovations in Semiconductor Engineering

The transistor race is no longer about shrinking gates—it’s about shrinking voltage and charge. 🔹 Today: strained-Si FinFETs at ~0.5 fJ/switch (still 10³× above Landauer). 🔹 Near-term: Ferroelectric “negative-capacitance” FETs slot straight into current CMOS lines—sub-60 mV swing, <10 aJ per toggle. 🔹 Next wave: Carbon-nanotube & 2-D MoS₂ channels → 1 aJ class, if we nail defect control. 🔹 Wildcards: Tunnel-FETs & spin-based MESO logic promise trick-low voltages but need drive current miracles. Bottom line: Chemistry is the new physics. Whoever masters exotic gate stacks and atom-thin channels first will unlock the attojoule era—and rewrite every energy roadmap from edge AI to hyperscale data centers. #Semiconductors #EnergyEfficiency #Nanotechnology #CMOSBeyond Chemistry Is Eating Moore’s Law: Chasing the Attojoule Transistor For half a century we squeezed performance out of transistors by carving ever-smaller features into silicon. That era is ending. Each extra etch step now costs billions—yet the energy per switch stubbornly hovers around 0.1–1 fJ, roughly a thousand times the fundamental Landauer limit. The next breakthroughs will come not from geometry but from chemistry. Here are the four plays that will matter: 1. Ferroelectric “Negative-Capacitance” FETs (2025–2027) By slipping a single doped-HfO₂ ferroelectric layer into the gate stack, foundries report sub-60 mV/dec slopes on silicon devices. That shaves the supply voltage toward 0.3 V and slashes dynamic energy below 10 aJ—all without abandoning 300 mm Si fabs. Expect pilot lines inside the next two node launches. 2. Carbon Nanotube & 2-D Channels (late-2020s) Aligned CNT sheets and monolayer MoS₂ deliver near-ballistic transport and textbook electrostatics in atom-thin bodies. Academic ring-oscillators already beat Si energy-delay products at 0.4 V. Once industry solves wafer-scale alignment and contact resistance, 1 aJ logic is feasible. 3. Quantum-Tunnelling TFETs III-V nanowire and van-der-Waals heterojunction TFETs dodge the 60 mV Boltzmann barrier entirely. Demonstrations show 30 mV/dec, but on-current is still 10–20× too low for mainstream logic. If materials scientists can lift drive currents without wrecking leakage, TFETs could operate at <0.2 V supply. 4. Spin & Magneto-Electric Devices MESO logic flips a ferro-magnet with a voltage and reads it via spin-orbit torque—non-volatile and projected at ~10 aJ per operation. The integration puzzle: marrying GHz spin devices to CMOS clocks and interconnect. The Hidden Hero: Backside and 3-D Integration Even with attojoule transistors, interconnect and memory dominate whole-chip energy. Foundries are therefore moving power rails to the wafer backside, stitching compute chiplets through glass interposers, and eyeing optical links for off-package I/O. Lower IR drop and shorter wires translate into system-level gains an order of magnitude larger than any single device tweak.

EPITAXIAL MONOLITHIC 3D INTEGRATION WITH LOWER-POWER 2D MATERIAL-BASED TRANSISTOR: WORLD'S FASTEST NOT MADE FROM SILICON The Moore era has been characterized by the continuous downscaling of Si integrated circuits, driving remarkable advancements in computing power and miniaturization. However, as Si-based devices approach their physical limits, challenges such as short-channel effects, increased power consumption, thermal dissipation, and quantum tunneling have raised concerns about the sustainability of Moore's Law. To address these limitations, the "More-Moore" era has focused on innovative strategies, including the integration of two-dimensional (2D) materials. Recognized for their high carrier mobility and superior gate control at atomic thicknesses, 2D materials offer significant potential for extending electronic performance. A key approach involves hybrid integration, combining 2D materials with Si-based circuits to overcome silicon's inherent constraints and sustain device scaling. In parallel, the "More-than-Moore" era envisions monolithic three-dimensional (M3D) integration, which enables higher device densities and multifunctionality. By layering electronic components in three dimensions, M3D integration offers a transformative approach to scaling, moving beyond the traditional reliance on silicon miniaturization. Integrating M3D CMOS systems with 2D materials-based n-type and p-type transistors presents significant technical challenges, requiring careful material selection and advanced fabrication techniques. Achieving high-performance M3D CMOS integration depends on the development of high-quality 2D p-type semiconductors, refinement of synthesis methods, precise interface engineering, and effective defect control. A team of Chinese scientists at Peking University may have turned the computing industry with their groundbreaking innovation. Using a thin sheet of lab-grown Bismuth and an architecture entirely distinct from today’s silicon-based chips, they have developed what they claim is the world’s fastest and most efficient transistor. This next-generation transistor not only surpasses the performance of leading processors from Intel and TSMC, but also operates with significantly lower energy consumption. According to their statement, at ångström-scale nodes, a gate-all-around (GAA) field-effect transistor (FET) utilizing two-dimensional (2D) semiconductors offers superior electrostatic gate control, enabling ultimate power scaling and enhanced performance. Their study reported successful development of a wafer-scale, multi-layer-stacked, single-crystalline 2D GAA configuration, achieved through low-temperature monolithic three-dimensional (M3D) integration, implying Pt and Au metal gates. The high-mobility 2D semiconductor Bi₂O₂Se was epitaxially integrated with a high-κ layered native-oxide dielectric Bi₂SeO₅, forming an exceptionally smooth interface. # https://lnkd.in/gUG3cKYR

🔴 TSMC, Cornell University, and Advanced Semiconductor Materials Co., Ltd. present the blueprint for next-gen semiconductor metrology in #NatureCommunications. The paper "3D atomic-scale metrology of strain relaxation and roughness in Gate-All-Around transistors via electron ptychography" proves that evaluating sub-5 nm #GAA architectures requires seeing beyond 2D projections to truly understand the atomic interfaces defining the next decade of #Semiconductor #Metrology. While conventional STEM struggles with multiple scattering depth artifacts, this team utilizes Multislice Electron Ptychography (#MEP) to reconstruct the 3D atomic potential of prototype GAA devices from a single 4D-STEM dataset. 1️⃣ Overcoming the Projection Limit: #Multislice #Ptychography By modeling multiple scattering and channeling effects, MEP achieves a lateral resolution of 0.49 Å and an axial blur of just 40 Å. Remarkably, it accomplishes this using only half the electron dose of conventional methods. 2️⃣ The Over 40% Strain Problem: #AtomicScale #StrainMapping In a 5 nm silicon channel, interfaces dominate. By tracking individual atoms in 3D, researchers found Si-Si spacing takes four bilayers (11 Å) to relax to its bulk value. Consequently, over 40% of the ultrathin channel remains actively under strain, fundamentally altering carrier mobility. 3️⃣ Decoding #InterfaceRoughness: Exponential vs. Gaussian MEP directly maps buried interface roughness, revealing stark asymmetries. The top interface (Si-on-SiGe) is smoother with an exponential roughness distribution, while the bottom interface (SiGe-on-Si) suffers from mouse-bite defects and follows a Gaussian distribution. 💡 My Take: As we push into the Angstrom era, the gap between process engineering and metrology is rapidly closing. In my own research controlling interfacial defects in InGaN/GaN Micro-LEDs, I constantly see how hidden morphological variations, like the strain and mouse-bites identified here, silently bottleneck performance. MEP's ability to decouple strain and roughness in 3D without destroying the local context is a massive leap for process diagnostics. What are your thoughts on integrating 4D-STEM metrology into early-stage high-volume manufacturing? 👇 Link in the comments #AdvancedPackaging #MooreLaw #MoreThanMoore #HardwareArchitecture #YieldEngineering #Manufacturing #Automation #3DIC #WaferLevelPackaging #HeterogeneousIntegration #DataCenter #AIHardware #FinFET #Nanotechnology #TCAD #AngstromEra #ElectronMicroscopy #4DSTEM #DefectAnalysis #MaterialScience Intel Corporation Samsung Electronics SK hynix America NVIDIA AMD Applied Materials Lam Research ASML Tokyo Electron US KLA ZEISS Group Thermo Fisher Scientific Oxford Instruments plc

⚡ Why are 3nm and 2nm Nodes So Difficult to Manufacture? The race to 3nm and 2nm technology nodes is one of the biggest milestones in semiconductor history. Each new “node” packs more transistors into the same area, but shrinking below 5nm pushes physics, materials, and manufacturing to their limits. Here’s a comprehensive breakdown: 🔬 1. Physics Limitations at the Atomic Scale • At 2nm, gate lengths are just 10–15 silicon atoms wide. • Quantum tunneling: Electrons can leak through ultra-thin gate oxides. • Short-channel effects degrade transistor control. • Traditional FinFETs are no longer sufficient — requiring new device architectures like Gate-All-Around (GAAFETs). 🏗 2. Device Architecture Challenges • FinFET → GAAFET transition: • GAAFETs use nanosheets/nanowires to fully wrap the gate. • More control, less leakage — but very hard to fabricate with atomic precision. • Variability sensitivity: A few atoms’ difference in channel thickness can change performance significantly. 🔎 3. Lithography Barriers • Extreme Ultraviolet Lithography (EUV) at 13.5nm wavelength is required. • At 2nm, even EUV faces: • Stochastic defects (random missing/extra patterns). • Mask 3D effects that distort features. • Multiple patterning steps add complexity, cost, and yield risk. ⚡ 4. Materials & Interconnects • Copper resistance skyrockets at nanoscale → delays signal transmission. • New materials like cobalt, ruthenium, or graphene are being explored. • Contact resistance (between transistor and interconnect) is now a major bottleneck. 🔋 5. Power & Heat Density • More transistors → more heat in the same area. • Advanced cooling and power delivery networks are required. • Even slight hotspots can reduce reliability dramatically. 🏭 6. Manufacturing Complexity & Yield • Each wafer at 3nm/2nm can cost $20,000+. • Billions of transistors → even a tiny defect rate kills yield. • Ultra-clean fabs, advanced process controls, and AI-driven inspection are essential. 📈 7. Cost & Ecosystem Barrier • Fab construction: > $20–25B per plant. • Design cost for a 2nm chip: $500M+. • Only a handful of companies (TSMC, Samsung, Intel) can afford it. 🔮 The Future Beyond 2nm Chiplets + advanced packaging (2.5D/3D stacking) will complement scaling. New materials (graphene, CNTs, 2D semiconductors) may take over silicon eventually. 3nm & 2nm aren’t just about smaller transistors → they’re about rethinking architecture, materials, and design to keep Moore’s Law alive. 🏁 Takeaway The difficulty of 3nm and 2nm is not just shrinking — it’s about fighting the laws of physics, managing astronomical costs, and inventing entirely new device architectures. That’s why each step forward is a revolution, not an evolution. #Semiconductors #2nm #3nm #MooresLaw #ChipDesign #SemiconductorManufacturing #Nanoelectronics #18/30 #30daychallenge

What's next for chips beyond 2nm?   The semiconductor industry is fairly certain how to design and make new chips at least until 2030, but there is some uncertainty beyond that point. Beyond 2030, the semiconductor industry could extend today’s technologies or migrate to something new. For example, in R&D, the industry is working on several futuristic transistor candidates, such as 2D FETs, CFETs and others, to enable new, advanced chips in the distant future. Chiplets is also an emerging option.   The latest developments on these technologies were presented in various papers at this week’s IEEE International Electron Devices Meeting (IEDM) in San Francisco.   Transistors, a key building blocks in chips, are tiny structures that serve as a switch in devices. Advanced chips each have billions of transistors.   For years, chips mainly consisted of planar transistors. Planar transistors are still used in today's chips, but they have certain limitations.   In response, Intel in 2011 migrated to a new, high-performance transistor called finFETs. Intel and others soon shipped various chips, such as GPUs and processors, using finFETs.   Now, finFETs face some limitations. So starting at the 3nm or 2nm nodes, the semiconductor industry will embrace a new transistor technology called gate-all-around (GAA). At 3nm, Samsung recently manufactured and shipped the world’s first chips based on a GAA transistor technology called nanosheet FETs. In R&D, Intel and TSMC are also developing nanosheet FET processes at 2nm.   Nanosheet FET transistors are expected to extend to the 14A node in 2027/2028, but they may reach the limit at the 10A node in 2029, according to a presentation from TEL at IEDM. What’s next? The industry has proposed several new transistor types on the roadmap, but nothing is concrete. The futuristic transistor types face several manufacturing and cost challenges. For now, though, the next transistor type on the roadmap is called complementary FETs (CFETs). CFETs could appear at the 10A node in 2029, according to TEL. At IEDM, Imec, Intel, Samsung and TSMC presented papers on CFETs. Intel demonstrated a CFET with a 60nm gate pitch. “Our most scaled devices consist of 3 nMOS on top of 3 pMOS nanoribbons with 30nm vertical separation," said Marko Radosavljević from Intel in a paper at IEDM. CFETs may extend to the 3A node in 2035, according to TEL. Then, the industry could move to 2D-based transistors, which incorporate transition metal dichalcogenide channel materials. At IEDM, TSMC presented a paper on a 2D device with a 12nm nMOS contact length and a 10nm gate length.   Other futuristic technologies are also in R&D, such as carbon nanotube FETs and Forksheet FETs.   There are other options that are available today. Some are currently shipping devices using chiplets, which integrates different dies in a package. Chiplets will play a big role in the future.  

Could the next revolution in chipmaking be not about shrinking transistors, but reinventing how we etch them? A few things are happening: Researchers at a major U.S. national lab are developing the Big Aperture Thulium (BAT) laser, a petawatt-class system built to supercharge extreme ultraviolet (EUV) lithography. This could be the spark that powers a ‘beyond-EUV’ wave. Today’s EUV tools use CO₂ lasers firing at tin droplets to generate plasma that emits 13.5 nm light, key for printing transistors at the 3 nm node and below. These systems gulp a staggering 1,400 kW just to run. BAT changes the game. It uses a 2 μm wavelength, which promises up to 10× better energy conversion, thanks to more efficient plasma formation and diode-pumped solid-state optics that manage heat far better than gas lasers. This isn’t incremental, it’s foundational. Imagine chips made faster, cheaper, while slashing energy costs. Think AI accelerators, fusion devices, quantum platforms, not just Moore’s Law. The infrastructure shift won’t be easy, and the industry’s cautious, but the science is persuasive. For those driving innovation: understanding this evolution in etch technology isn't optional, it’s critical. #Semiconductors #EUVLithography #NextGenChips #LithographyInnovation

The nano highways inside a chip are gridlocked. Time to separate the freight from the fast lane! 𝑴𝒆𝒆𝒕 𝒕𝒉𝒆 𝒊𝒏𝒕𝒆𝒓𝒄𝒐𝒏𝒏𝒆𝒄𝒕𝒔. 👇 This industry is racing toward ~1 trillion transistors per package by 2030 and the transistor evolution tells only part of that innovation story. We've gone from Planar to FinFET to Gate-All-Around pushing performance at the most advanced nodes. 𝐁𝐮𝐭 𝐭𝐡𝐞𝐧 𝐭𝐡𝐞𝐫𝐞’𝐬 𝐭𝐡𝐞 𝐰𝐢𝐫𝐢𝐧𝐠 𝐧𝐞𝐞𝐝𝐞𝐝 𝐭𝐨 𝐮𝐧𝐥𝐨𝐜𝐤 𝐭𝐡𝐞 𝐜𝐨𝐦𝐩𝐮𝐭𝐢𝐧𝐠 𝐩𝐨𝐰𝐞𝐫 𝐨𝐟 𝐚𝐥𝐥 𝐭𝐡𝐨𝐬𝐞 𝐟𝐚𝐧𝐜𝐲 𝐭𝐫𝐚𝐧𝐬𝐢𝐬𝐭𝐨𝐫𝐬. Interconnects make up the copper highways in a chip, moving power and signals around. 🛣️⚡️ Today's conventional approach is 𝐟𝐫𝐨𝐧𝐭 𝐬𝐢𝐝𝐞 𝐩𝐨𝐰𝐞𝐫 𝐝𝐞𝐥𝐢𝐯𝐞𝐫𝐲. That means power is delivered from the top of the chip, which requires the power highways to go through many layers of wiring to get to the transistors at the bottom of the stack. This means that precious chip real estate has to be used for power delivery, while power is lost as it travels through those many layers. 𝐁𝐚𝐜𝐤 𝐬𝐢𝐝𝐞 𝐩𝐨𝐰𝐞𝐫 𝐝𝐞𝐥𝐢𝐯𝐞𝐫𝐲 flips the script and routs power delivery from the bottom (or ‘back side’) of the chip, gaining more direct access to the transistors. In return, the ‘front side’ real estate can be used to increase transistor density, while improving the overall power and performance of the chip. But as with any innovation: if it was easy, everybody would be doing, right? This innovation will be implemented by the world's top chipmakers in their most advanced chip nodes over the coming time and requires collaborative effort across the semiconductor manufacturing ecosystem, including in deposition, etch, chemical mechanical planarization, bonding, wafer thinning, and more. // 📫 Join the Curious Clan! Subscribe for free to my weekly newsletter Always Be Curious. The link's up there, just under my name. 🔗 You’ll get the now, how and wow of science and tech, with a special focus on the chip industry. Every Sunday morning. ☕️🥐

I am deeply intrigued by this slides. Out of the 1000X performance improvement Nvidia gain in last 10 years, only 2.5X came from process improvement. Moore's Law has long been synonymous with the progress of semiconductor technology, predicting the doubling of transistors on a microchip approximately every two years. However, as we navigate the intricacies of the 21st century, it becomes evident that the traditional semiconductor process driven advancements is not sustained. To live the Moore's law, semiconductor manufacturing process improvement is not the answer any more, the needed improvement will come from design. So this is the era for our Designers. Particularly domain specific computing (or called Domain Specific Architectures) will be the answers. out of the 1000X improvement， ~16x come from number represenation!. The data representation are so different for different domain of applications. No more one size fits all data types. Domain specific data type will drive the new architecture. This is for AI computing, this is for wireless computing, this is for video/crypto computing. It will all come with their specific data width, dynamic range, precision requirement, complex or real data source. This is a gold mine for our next level of optimizations. Come nexts is the complex instructions, 12X!. This is a bit against the recent RISC (not RISC-V) movement. It was shown in Nvdia GPU design (as quote in the slide ) and it is also in the wireless specific computing（ remember long time ago there was a Qualcom paper on Hexagon DSP to combine ~30 RISC instruction to one to perform FFT computing which is fundamental for wireless computing) This reduce the code fetch, decode energy from 30 instructions to ONE. (while the execution is also optimized to it's specific addressing/computing mode for this FFT computing) Domain-specific architecture marks a departure from the one-size-fits-all approach. Instead of merely cramming more transistors onto a chip, designers are now crafting architectures tailored to specific tasks. This approach optimizes efficiency, enabling hardware to excel in particular domains such as artificial intelligence, graphics rendering, or scientific simulations. The trajectory of technological advancement is no longer solely dictated by the shrinking size of transistors. It's about reimagining the very architecture that drives our devices. As we gaze into the future, domain-specific architecture stands as a beacon, guiding us towards a realm where innovation is not confined by the constraints of a standardized approach. Moore's law is not dead, long live the designer's aspiration and pursuit.

imec Expands Semiconductor Roadmap with 2D Materials IMEC, a leading semiconductor R&D institute, is incorporating 2D materials into its logic scaling roadmap. A recent article by César Javier Lockhart de la Rosa, IMEC’s program manager for exploratory logic, explores the challenges and potential of transition metal dichalcogenides (MX₂) as a channel material for gate-all-around (GAA) transistors. IMEC has already contributed significantly to transistor scaling, supporting the industry’s shift from FinFET to GAA nanosheets and advancing backside power delivery. Its next focus is complementary FETs (CFETs), expected from the A7 node onward, extending its roadmap to A3 (circa 2035). To prepare for 2D material adoption, IMEC is researching their use in low-performance transistors before scaling to advanced nodes. Key challenges include deposition techniques, doping, dielectric integration, low-resistance contacts, and cost considerations. IMEC has demonstrated a successful MX₂ dry transfer process, presented at the 2024 VLSI Symposium. Could 2D materials be the next step in extending Moore’s Law? #Semiconductors #IMEC #2Dmaterials #LogicScaling #GAA #CFET #ChipDesign,#SemiconductorManufacturing, #VLSI, #Lithography, #ICPackaging

Some encouraging Intel technology announcements… It is great to see Intel put its technology roadmap with several interesting announcements. While we are focus on injecting new capital in semiconductor Industry to build capacity, we should not take our foot off the technology gas pedal. This is the best way to stay ahead of the competition. Several innovations stood out: Intel’s latest transistor research shows an industry first: the ability to vertically stack complementary field effect transistors (CFET) at a scaled gate pitch down to 60 nanometers (nm) Intel’s PowerVia will be manufacturing-ready in 2024, which will be the first implementation of backside power delivery. Intel shows advancements in process integration of silicon and GaN. Intel has now successfully demonstrated a high-performance, large-scale integrated circuit solution – called “DrGaN” – for power delivery. Certainly worth a read. Article: What’s New: Today, Intel unveiled technical breakthroughs that maintain a rich pipeline of innovations for the company’s future process roadmap, underscoring the continuation and evolution of Moore’s Law. At the 2023 IEEE International Electron Devices Meeting (IEDM), Intel researchers showcased advancements in 3D stacked CMOS (complementary metal oxide semiconductor) transistors combined with backside power and direct backside contacts. The company also reported on scaling paths for recent R&D breakthroughs for backside power delivery, such as backside contacts, and it was the first to demonstrate successful large-scale 3D monolithic integration of silicon transistors with gallium nitride (GaN) transistors on the same 300 millimeter (mm) wafer, rather than on package. Rest of the article Link: https://lnkd.in/gZUifzVx