Common Issues in Custom High-Voltage System Design

Why Most SiC #Inverter Failures Are Layout Failures Forget blaming the #SiC die or the gate driver. At hundreds of volts and hundreds of amps, the thing that actually breaks is almost always copper and geometry, not silicon. At 800 V and multi-hundred-kW power levels, parasitics stop being “second order.” A few nanohenries of DC-link loop inductance will ring with device capacitances and kick V_DS into catastrophic overshoot at turn-off. We’ve repeatedly seen systems spike well beyond the rail simply because the caps and busbars weren’t essentially welded to the half-bridge. Key failure mechanisms I keep seeing in the lab and field: • DC-link loop inductance → huge overshoot. Any length in the high-current loop stores energy that gets dumped into the MOSFET at turn-off. Tighten that loop first. • Gate ↔ power loop coupling → false turn-on. Fast dv/dt pumps current through Miller capacitances. If the gate loop is loose, you get brief gate-source glitches that are enough to trigger shoot-through on SiC. • Uneven current sharing and resonances. Paralleled devices double di/dt but any trace-length mismatch produces a device that hogs the surge. Common-source inductance feeds back into timing and creates deterministic imbalance. • “Random” failures aren’t random. Simulators often under-represent parasitic loops. What looks safe on paper rings differently once copper, assembly tolerances, and temperature swing appear. Teams often react by tweaking gate resistances or adding snubbers. Those are band-aids. The real fix is architectural: design the switching cell and the power loop first, then pick devices. Practical design priorities that actually stop crashes: • Minimize DC-link loop L with laminated/balanced busbars • Place low-ESR bulk and HF caps millimetres from the half-bridge • Make gate loops ultra-compact and electrically isolated from power loops • Keep parallel device source inductance matched and symmetric SiC enables extreme switching, but it also exposes every #PCBLayout failing. If your inverter explodes on first power, don’t start by blaming the MOSFET. Rework the copper. Reliable SiC inverters start with power-loop architecture and layout, not the transistor. Image credit: EEWorld. The inverter shown is the #Hyundai IONIQ 5 800 V traction inverter, used here as a representative example of modern high-power SiC inverter layout. #PowerElectronics #InverterDesign #ReliabilityEngineering #ElectricVehicles #HighPowerDensity #MotorDrives

If you have ever written or reviewed a high voltage circuit breaker specification, you know the standards are dense. IEC 62271-100, ANSI/IEEE C37.04, C37.06, C37.09. But not all ratings carry equal weight. Most breaker specs look complete, but hey are not. A few critical ratings consistently cause the most confusion, the most procurement errors, and the most surprises during commissioning. Here are the ones I pay the closest attention to, explained. Rated short-circuit current. The interrupting rating is stated on a symmetrical RMS basis, but the application still has to be checked for asymmetrical duty and DC offset. In high X/R systems, the actual interrupting duty can exceed what a superficial nameplate check suggests. I have seen specifications where this was not verified until the fault study came back. Transient Recovery Voltage. TRV is one of the most overlooked and most consequential ratings. After the breaker clears the arc, the system imposes a recovery voltage across the contacts. If that voltage rises faster than the breaker's dielectric recovery, restrike occurs. The standard provides TRV envelopes for different fault types, but the actual system TRV depends on your network topology, transformer impedance, cable lengths, and grounding. Blindly copying standard TRV values into a spec, especially for non-standard duties or unusual network configurations, is a serious mistake. Close and latch current. This is the peak asymmetrical current the breaker must withstand when closing onto a fault. It is not the same as the interrupting rating. If the breaker is used in reclosing service, this becomes especially important, because it may have to close into a fault that has not cleared. Specifying the interrupting capability without verifying close and latch for your application can leave a real gap. Continuous current and ambient temperature. The continuous current rating assumes a defined ambient and installation condition. In hot climates, poorly ventilated enclosures, or high-density switchgear lineups, actual temperature rise can exceed what the rating assumes. This should be addressed in the specification, not discovered during installation. Dielectric strength and altitude. The breaker insulation level has to match the application, including power-frequency withstand, lightning impulse withstand, and where applicable, switching impulse withstand. Above 1000 meters, air density drops and dielectric withstand decreases. If your substation is at elevation, the specification must account for it. A well written breaker specification is not a copy of the standard. It is an engineering document that translates system conditions into equipment requirements. What is the most common gap you have seen in breaker specifications? And if you have experienced a TRV-related failure, I would be very interested to hear about it.

40V–400V High-Side Current Sensing: In high-side current sensing, the difficult part is often not the shunt voltage itself. The shunt voltage is usually small and the harder part is that this small differential signal may sit on top of a very large common-mode potential. That is what makes 40V–400V high-side sensing very different from ordinary low-voltage current measurement. 🟡 The signal is small, but the common-mode level is high In this kind of circuit, the voltage across the shunt resistor may still be only a small differential value. But that small signal is riding on a bus voltage that may be tens or hundreds of volts above ground. So the real problem is not only how to measure Vsense. It is how to measure it while the entire sensing point sits at a very high potential. 🟡 This example is useful because it shows one way to handle the front-end reference A normal low-voltage op amp cannot simply be placed into this kind of path in the usual ground-referenced way. In this example, the front-end is arranged so that the op amp operates near the high-side potential instead of directly working from the low-side ground reference. 🟡 This does not mean the op amp directly produces an MCU-ready low-side signal What this kind of front-end does is make the high-side sensing stage workable under large common-mode conditions. The signal still has to be transferred through the rest of the circuit into a form that the downstream monitor can use. So this should be understood as a front-end handling method, not as a complete shortcut around level translation. 🟡 Once the front-end works, other constraints appear immediately After the common-mode issue is handled, the real work still includes: • zener bias current • resistor sizing • static dissipation • PMOS voltage stress and power loss • behavior over voltage and temperature So even when the principle is clear, the implementation still has practical electrical and thermal limits. 🟡 PCB layout is part of the sensing solution At this voltage level, schematic correctness is not enough. The board still needs: • clear separation between high-voltage and low-voltage regions • careful shunt routing • attention to creepage, clearance, and thermal behavior A workable topology can still become a poor hardware solution if layout does not respect the voltage conditions around it. This is best treated as a design example, not a universal recommendation. This kind of non-isolated approach is worth studying because it helps explain one way to deal with a large common-mode problem in the analog front end. But that does not mean it is automatically the preferred solution for every modern 400V system. In many industrial or automotive 400V systems, galvanic isolation is still the more typical choice for safety and compliance reasons. #PCB #AnalogDesign #CurrentSensing #HighSideSensing #HardwareEngineering #ElectronicsEngineering #SignalConditioning #PowerDesign #PCBDesign #KnownPCB

Converter Passes Conducted EMI but Fails Radiated EMI – Why This Happens? A question I often see during EMC testing: “Our converter passes conducted emissions, but fails radiated EMI. How is that possible?” Passing conducted EMI means your filtering, grounding, and line impedance control are doing their job on the power lines. Radiated EMI, however, is a different challenge altogether. Common reasons for radiated EMI failure: *High di/dt & dv/dt loops Fast switching edges create strong magnetic and electric fields, especially from poorly controlled current loops. *PCB layout issues Long gate loops, poor return paths, split ground planes, or large high-frequency current loops act as unintended antennas. *Cables behaving as antennas Motor cables, DC links, sensor wires, or even short harnesses can efficiently radiate noise above ~30 MHz. *Inadequate shielding strategy Passing conducted EMI doesn’t guarantee the enclosure, seams, vents, or cable entry points are RF-tight. *Common-mode noise dominance Radiated emissions are often driven by common-mode currents, not differential-mode noise that line filters typically address. Key takeaway: Conducted EMI ≠ Radiated EMI compliance Radiated EMI is primarily a layout, geometry, and field-coupling problem, not just a filtering problem. Typical fixes I see working in practice: ✔ Optimised PCB stack-up and HF current loops ✔ Gate drive edge-rate control ✔ Common-mode chokes and cable ferrites ✔ Shielded cables with 360° termination ✔ Better enclosure bonding and grounding EMC success is not about “adding more filters” — it’s about controlling where the energy flows. If you’re designing high-power converters, inverters, or fast-switching SMPS, always think EMI early in the design, not at the test lab.

High voltage power module is the building block for our future power grid involving HVDC & MVDC, advanced transportation systems, and various types of renewable energy systems. The development of SiC technology provides more opportunities and challenges to the HV module development for future energy conversion. Silicon carbide (SiC) power modules have been demonstrated potential for improving power density and efficiency for low-voltage power electronics systems. However, designing MV/HV SiC power modules involves significant design challenges due to higher blocking voltage and exacerbation of side effects due to high switching dv/dt and di/dt of SiC devices-concerns that may not be as critical as in low-voltage module development. This article reviews the development of state-of-the-art MV/HV SiC power modules, ranging from 3.3 kV to 40 kV, from both industry and academia. In the first part of this paper, a discussion on SiC modules based on voltage level is presented. This is followed by a discussion of challenges associated with designing and testing MV/HV modules- including parasitic controls, electromagnetic interference (EMI), partial discharge, and thermal management-and the corresponding mitigation approaches from various perspectives. We conclude with a summary of major findings and future directions for the development of MV/HV modules.

High Voltage Busbar Designing using Ansys Designing high-voltage busbars is critical for ensuring efficient and safe power distribution in electrical systems. This process involves careful consideration of thermal, electrical, and mechanical properties to optimize performance and minimize risks. Using simulation packages for the thermal and coupled analysis of Ansys, the following simulation was carried out as shown in the image. 1) Thermal characteristics: Thermal characteristics are essential in busbar design, as high currents generate heat due to resistance. Effective heat dissipation is crucial to prevent overheating, which can lead to insulation failure and reduced lifespan. Materials with high thermal conductivity, like copper and aluminum, are commonly used to ensure rapid heat transfer. Thermal analysis also considers environmental factors such as ambient temperature and mechanisms like forced air or liquid cooling. 2) Current Carrying Capacity: The current carrying capacity of a busbar is determined by its cross-sectional area, material resistivity, and operational conditions. Proper sizing is essential to avoid excessive heating. Designers must account for peak current demands and continuous operating currents. Standards such as IEC or ANSI provide guidelines to calculate ampacity based on parameters like skin effect, proximity effect, and environmental conditions. 3) Thermal stresses: High currents and frequent load fluctuations cause busbars to expand and contract. These cyclic stresses can lead to material fatigue, mechanical deformation, or joint failures. Expansion joints or flexible connectors are often integrated into busbar systems to mitigate these effects. Additionally, selecting materials with low thermal expansion coefficients can help maintain dimensional stability. 4) Effect of High Voltage and Induced EMF on Busbar: High voltage introduces challenges such as dielectric breakdown, corona discharge, and electromagnetic interference (EMI). Proper insulation design, including the use of high-grade insulating materials and adequate creepage and clearance distances, minimizes these risks. The induced electromagnetic fields (EMFs) due to high voltage and current can cause eddy currents and heating in nearby conductive components. Shielding and strategic placement of busbars help reduce these effects, ensuring system stability and efficiency. In conclusion, designing high-voltage busbars requires a multidisciplinary approach balancing thermal management, electrical performance, and mechanical integrity. Proper analysis and adherence to industry standards ensure reliability, safety, and longevity in high-voltage applications. . . . #HighVoltage #BusbarDesign #ElectricalEngineering #ThermalManagement #PowerDistribution #EnergyEfficiency #CurrentCarrying #ThermalStress #EMFEffects #ElectricalInsulation #PowerSystems #HighVoltageEngineering #ElectricalSafety #EnergySolutions #EngineeringDesign

Common Issues Faced in H-Bridge of AC/DC (PSPWM and LLC) at operating Frequencies from 100 kHz to 250 kHz: 1. Dead short of high-side and low-side MOSFETs in no time:  a. Ensure that the low-side MOSFETs are in the ON state during the PWM OFF state to keep the boost strap cap at charged state.  b. Check for sufficient dead time. Higher gate resistance can cause overlap in high-side and low-side gate pulses, leading to shoot-through.  c. Ensure sufficient bootstrap capacitance to hold the gate voltage during the turn-on of the high-side MOSFET.  d. Verify that Vds ringing is within the MOSFET's limits. (Ideally, design to keep ringing at Vds to no more than 5% to get through EMI/EMC)  2. Leading leg S1 and S4 overheating in PSPWM.  3. Overheating of S4 alone.  4. Overheating of S1 and S4 under no-load conditions, but less loss under loaded conditions.  5. Overheating at the secondary-side MOSFET.  (problems from 2 to 5 requires clear understanding on switching sequence of both pri and sec Mosfets, optimized switching pulse, topology and proper magnetics design. Additional Notes:  Using an analog PWM controller may not offer much flexibility in adjusting the PWM. Implementing the PWM in a microcontroller requires careful attention to the sequence of how the PWM is turned ON and OFF, as this matters significantly.  (source of Image: https://lnkd.in/gg3cSQXC) #PowerElectronics #EVTechnology #EVCharger