Sreekanth Boga

*** Silent Killer in High-Speed Interface Design *** Every engineer working on PCIe, USB, CSI, DSI, LPDDR, SerDes, or any high-speed interface knows: "Timing closure will keep you Up at night." But here’s the thing—It is not always the big violations that kill a design. These can be found and fixed. The silent killers are the marginal cases: * That one Async Clock Domain Crossing that looked fine… until Silicon. * That Power mode Transition that only happens under rare Conditions. * That Corner case in Equalization that only fails in a specific voltage/temp combo. "These don’t show up in the standard verification flow. You have to hunt them down." What’s your approach to catching these hidden pitfalls?

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Alignment across teams is everything. Leading verification teams across the U.S., India, Ireland, and Taiwan has reinforced one key lesson: Talent is everywhere, but alignment drives success. 🔹 Communication is the biggest challenge—without clear documentation, async teams struggle. 🔹 Unified verification methodologies are essential—disparate approaches slow progress. 🔹 Remote coordination is an art—effective planning, tooling, and risk mitigation make or break project schedules. To solve these challenges, I built and scaled a global verification council to unify methodologies across teams. The result? Sharing of learnings, Faster debug cycles, higher first-pass success rates, and a streamlined development pipeline. How do you ensure seamless collaboration across time zones and disciplines?

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What does acceleration feel like to an engineer? On the left: hours lost to data prep and workflow restarts. On the right: that time reclaimed for modeling, testing, and shipping. Faster hardware doesn’t just cut tasks, it changes the shape of your day. Chapter 4 of The Codex report walks through the math and the culture shift that follows. 🔗https://lnkd.in/gGXhxe78 #theseus #VoltronData

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*** Problem With Verification Quality Metrics *** We track "Code coverage, Functional coverage, Assertions, Regression pass rates & Bug charts, religiously. But here is the uncomfortable truth: "A project can hit 100% on every metric and still have Silicon BUGs." Why? Because metrics only tell you where you have looked - not where the gaps are. I’ve seen teams get blindsided because they trusted the numbers without stepping back and asking: * “What failure modes aren’t we measuring?” ** “Where are we making assumptions instead of testing?” *** “Which failures are we detecting too late?” Great verification isn’t about chasing numbers. It is about "Asking the right Questions" before Tape-out starting with Testplanning. What is a verification gap you have seen catch teams off guard?

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*** First-Pass Silicon Success Starts Long Before Tape-out. *** People think First-Pass Silicon success is all about PERFECT Verification. But by the time you’re running final regressions, the outcome is already decided. The real difference? How early Verification THINKING gets embedded in the Design process. The best teams: * Bake verification Constraints into design quite Early. ** Align verification with Architecture Decisions, Not just RTL. *** Catch high-level MODELING errors before they become low-level Bugs. Silicon success is not won in the lab. It is won in the first few Weeks of a project. How early does verification gets involved in your design flow?

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𝗠𝗶𝘅𝘁𝘂𝗿𝗲 𝗼𝗳 𝗘𝘅𝗽𝗲𝗿𝘁𝘀 (𝗠𝗼𝗘): 𝗦𝗰𝗮𝗹𝗶𝗻𝗴 𝗟𝗟𝗠𝘀 𝗘𝗳𝗳𝗶𝗰𝗶𝗲𝗻𝘁𝗹𝘆 𝘄𝗶𝘁𝗵 𝗦𝗽𝗮𝗿𝘀𝗲 𝗖𝗼𝗺𝗽𝘂𝘁𝗮𝘁𝗶𝗼𝗻 Large Language Models (LLMs) continue to grow in size, pushing the limits of AI capabilities but also introducing challenges in cost, memory, and inference speed. Mixture of Experts (MoE) offers an innovative approach by using sparse computation, activating only a subset of parameters per input. Let's explore recent advances in MoE architectures and how models like DeepSeek-v2 and DeepSeek-v3 are optimizing efficiency. 🔹 𝗖𝗵𝗮𝗹𝗹𝗲𝗻𝗴𝗲𝘀 𝗶𝗻 𝗠𝗼𝗘: 𝗥𝗼𝘂𝘁𝗶𝗻𝗴 𝗕𝗼𝘁𝘁𝗹𝗲𝗻𝗲𝗰𝗸𝘀 & 𝗣𝗲𝗿𝗳𝗼𝗿𝗺𝗮𝗻𝗰𝗲 𝗧𝗿𝗮𝗱𝗲-𝗼𝗳𝗳𝘀 While MoE improves efficiency, it also faces key challenges: 𝗧𝗼𝗸𝗲𝗻 𝗗𝗿𝗼𝗽𝗽𝗶𝗻𝗴 𝗶𝗻 𝗟𝗼𝗻𝗴 𝗦𝗲𝗾𝘂𝗲𝗻𝗰𝗲𝘀: OpenMoE struggles with routing stability, sometimes losing tokens in long sequences. Fixed Routing in Pretraining: Early routing patterns can be inefficient post-training. 𝗗𝗼𝗺𝗮𝗶𝗻 𝗦𝗵𝗶𝗳𝘁 𝗜𝘀𝘀𝘂𝗲𝘀: MoE models may struggle to generalize across different data distributions. A recommended solution is incorporating instruction-following data in pretraining to enhance routing adaptability. 🚀 𝗗𝗲𝗲𝗽𝗦𝗲𝗲𝗸 𝗠𝗼𝗘: Smarter Scaling for AI Models The DeepSeek series addresses these issues with innovative optimizations: 🔸 𝗗𝗲𝗲𝗽𝗦𝗲𝗲𝗸-𝘃𝟮: 𝟮𝟯𝟲𝗕 𝗣𝗮𝗿𝗮𝗺𝗲𝘁𝗲𝗿𝘀, 𝟮𝟭𝗕 𝗔𝗰𝘁𝗶𝘃𝗲 1️⃣ Multi-Head Latent Attention (MLA): Cuts memory use by 93% with efficient KV cache storage. 2️⃣ Fine-Grained Expert Allocation: Balances shared and specialized experts across devices. 3️⃣ Device-Level Load Balancing Loss: Ensures even routing across devices, improving stability. 🔸 𝗗𝗲𝗲𝗽𝗦𝗲𝗲𝗸-𝘃𝟯: 𝗔 𝟲𝟳𝟭𝗕 𝗣𝗮𝗿𝗮𝗺𝗲𝘁𝗲𝗿 𝗠𝗼𝗱𝗲𝗹 𝘄𝗶𝘁𝗵 𝗡𝗲𝘄 𝗘𝗻𝗵𝗮𝗻𝗰𝗲𝗺𝗲𝗻𝘁𝘀 1️⃣ Multi-Token Prediction (MTP): Predicts multiple tokens at once for better efficiency. 2️⃣ Auxiliary-Loss-Free Load Balancing: Dynamically adjusts expert selection without added inefficiencies. 3️⃣ FP8 Mixed Precision Training: Reduces training costs significantly (~$5.6M for full training). 4️⃣ Extensive Post-Training: Includes context extension (128K tokens), SFT, RLHF, and knowledge distillation. 📊 𝗞𝗲𝘆 𝗧𝗮𝗸𝗲𝗮𝘄𝗮𝘆𝘀 ✅ Trained with 2.78M H800 GPU hours ✅ Performance rivals top closed-source LLMs ✅ Practical, scalable MoE for real-world deployment 🔮 𝗧𝗵𝗲 𝗙𝘂𝘁𝘂𝗿𝗲 𝗼𝗳 𝗠𝗼𝗘: 𝗘𝗳𝗳𝗶𝗰𝗶𝗲𝗻𝘁 𝗔𝗜 𝗦𝗰𝗮𝗹𝗶𝗻𝗴 MoE is revolutionizing LLM training, making sparse computation viable at scale. While early MoE models had challenges, recent breakthroughs like MLA, MTP, and smarter load balancing are proving MoE's potential. DeepSeek-v3 shows that sparse models can match dense models, signaling a shift in AI scaling strategies. What’s your take on MoE architectures? Will they define the future of AI, or do dense models still have an edge? Let’s discuss! 👇 credit : Cameron R. Wolfe, Ph.D.

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Cadence and NVIDIA have achieved hardware-accelerated dynamic power analysis for billion-gate AI designs, running billions of cycles in just hours with up to 97% accuracy. Together, NVIDIA's accelerated computing expertise and Cadence's EDA expertise are advancing power profiling to help make accelerated computing platforms more efficient.

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The future of SoC verification is here... Calibre's 2nd-gen Verilog-to-LVS achieves up to 4X faster translation and 92% less memory use for SoC signoff. Get a look at the architecture powering advanced verification results in this paper available here

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Launch DevDuck, Bob, and your cloud-hosted Llama 4 Scout agent — all in one go with a simple Docker compose up. We are partnering with Docker, Inc to bring you Container-Native Multi-Agent AI. Powered by Cerebras wafer-scale inference (~2,600 tok/s) and Google’s Agent Development Kit. Try the demo today, scale in production tomorrow. Clone the repo: https://lnkd.in/g3V7huYZ

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From Silicon to Software: Week 12 The Software BOM: When the Build System Becomes the Product In hardware, a Bill of Materials (BOM) is table stakes. You don’t ship a board without knowing every resistor, capacitor, inductor, and IC. Every part has a number. Every vendor is documented. In software? Too many teams still treat the BOM as optional, a “nice-to-have.” Something compliance can worry about later. Here’s the problem: code doesn’t just run. It’s built. Toolchains, compilers, libraries, dependencies, environment variables, build scripts, CI/CD pipelines, all of it is part of the product, whether you admit it or not. Lose track of that, and you’re not managing a product anymore. You’re managing a gamble. I once had to update a shipping product so old it could’ve qualified for a museum exhibit. The CI/CD system had been shut down to “save resources.” Years later, a small regulatory change required a simple tweak. Easy, right? Just change a constant and rebuild. Except no one could. The pipeline was gone. The scripts were gone. The compiler only ran on an operating system that now needed a virtual machine to boot. We dug up old docs, patched drivers, and found someone who still remembered how to install the tools, like summoning a retired wizard for one last spell. The code change took five minutes. The archaeology took three weeks. That’s not maintenance. That’s engineering by hope, not design. And this is why a Software Bill of Materials (SBOM) isn’t just about open-source compliance or checking a regulatory box. It’s about survival. Knowing what’s in your code is only half the battle, you also need to know how it was built, with what, and whether you can rebuild it when the next regulator, auditor, or customer comes knocking. The smartest teams I’ve seen treat the build system itself as part of the product: • Capture compilers, libraries, and dependencies in containers. • Version CI/CD scripts alongside the code. • Automate reproducible builds so no one has to remember ancient flags. • Archive toolchains and build artifacts as first-class deliverables. Because hardware fails loudly: you can smell a burnt resistor, you can see the magic smoke wafting in the air. Software fails silently. You don’t realize you’ve lost the ability to build until the moment you need it and by then, the cost is measured in weeks, not hours. An SBOM isn’t a file. It’s the difference between a product you can support for decades and one you hope no one ever asks you to touch again. If your product’s longevity depends on the software, then your dependencies and build system are part of the product. Treat them that way. How does your team handle this? Do you keep your build environments alive, or do they quietly fade away after launch day? #FromSiliconToSoftware #embedded #software #sbom #maintenance #cicd

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With NVIDIA Alpamayo, autonomous vehicles are learning to reason, not just react. Learn more about how NVIDIA Alpamayo is accelerating the development of AV technology in this Hugging Face post, penned by Marco Pavone, Director of Autonomous Vehicle Research at NVIDIA. 🔗 Read the blog: https://bit.ly/3Z3kvzI 🚗 Check out the model: https://bit.ly/3Z0IiQL

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Get a deep dive into multi-device programming on Tenstorrent hardware. In this session, Sr. Engineer Tapasvi Patel covers how to use our compiler TT-Forge™ for device meshes, tensor sharding, and collective communications. Watch here --> https://lnkd.in/e8PhsuQ3

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Almost exactly 3 years ago I was privileged to stand on stage in Santa Clara and announce the first wave of AI for verification. Today we make probably the most exciting announcement since then! Really excited to work with the ChipStack team as we define and develop Agentic AI for IC development together! ~~ We’re excited to announce that ChipStack, a pioneer in agentic AI for chip design and verification, is joining Cadence. ChipStack’s generative AI-driven platform helps accelerate design and verification workflows through deep design understanding, intelligent test planning, test generation, and AI-assisted debugging. Why this matters for our customers: ✅ Accelerated Verification – Move from weeks to days for front end IC design. ✅ AI-Powered Productivity – Scale without proportional headcount. ✅ Unified Flow – ChipStack’s generative AI agents will integrate seamlessly into Cadence’s Agentic AI and EDA solutions. ChipStack brings deep expertise in AI-driven design understanding, intelligent test planning, and AI-assisted debugging—strengthening our commitment to innovation and time-to-market acceleration. 👉 Read blog: https://ow.ly/NX2E50XpxZI #ChipStack #AI #Semiconductor #Design #Verification

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🚀 Socionext Breaks New Ground with 3DIC & 5.5D Packaging Socionext has officially taped out a next-gen SoC using TSMC’s SoIC-X 3D stacking—combining N3 compute and N5 I/O dies in a face-to-face (F2F) configuration. This milestone slashes latency, boosts bandwidth, and cuts power consumption, redefining what's possible in consumer, AI, and HPC applications. With support for chiplets, 2.5D, 3D, and now 5.5D packaging, Socionext is leading the charge in heterogeneous integration—bringing together multiple tech nodes and functions in a single, high-density package. 🔧 Vertical stacking. ⚡ Lower power. 📦 Smaller footprint. 💡 Limitless potential. #Semiconductors #3DIC #SoC #Innovation #Socionext #TSMC #AI #HPC #ChipDesign #TechLeadership #Hiring #Semiconductorhiring #ASIC #Marketing #TPM #Technicalprogrammanager(s) #SFBAYAREAJobs

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