Pranav Tipnis

*** Silent Killer in High-Speed Interface Design *** Every engineer working on PCIe, USB, CSI, DSI, LPDDR, SerDes, or any high-speed interface knows: "Timing closure will keep you Up at night." But here’s the thing—It is not always the big violations that kill a design. These can be found and fixed. The silent killers are the marginal cases: * That one Async Clock Domain Crossing that looked fine… until Silicon. * That Power mode Transition that only happens under rare Conditions. * That Corner case in Equalization that only fails in a specific voltage/temp combo. "These don’t show up in the standard verification flow. You have to hunt them down." What’s your approach to catching these hidden pitfalls?

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*** Interconnect Challenge in Chiplet-Based SoCs *** A well-designed Chiplet-Based SoC isn’t just about partitioning logic across multiple dies—it’s about how those dies communicate. Die-to-Die (D2D) interfaces such as UCIe, BoW, AIB, AMD Infinity Fabric, Intel EMIB, TSMC CoWoS—all these approaches tackle the same fundamental question: 👉 How do we maintain High bandwidth, Low latency, and Low power across chiplet boundaries? Unlike monolithic SoCs, where interconnects are internal, chiplet architectures require: o Standardized interfaces to mix and match chiplets from different vendors. o Efficient serialization to avoid unnecessary power consumption. o Latency-aware partitioning to ensure real-time workloads don’t suffer. The move to chiplets is a paradigm shift in interconnect design. The challenge is making it seamless. For those working with multi-die architectures, what’s been the hardest part of optimizing inter-chiplet communication?

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Excited to share Synopsys Inc first-pass silicon success on TSMC's N2 for MIPI and USB IP. This is a key milestone for AI-enabled edge devices on GAA nanosheet technology. Our customers can speed their time to market with our IP solutions for TSMC's N2 and N2P designs. Looks at these excellent results below, and learn more on our recent blog: https://lnkd.in/gyj3zVAJ

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Big news from Micron today—this marks a pivotal moment in our mission to advance U.S. semiconductor leadership. We’re expanding our U.S. investments to approximately $200 billion, reinforcing our long-term commitment to domestic memory manufacturing and R&D. This includes: - A second leading-edge memory fab in Boise, Idaho—complementing the high-volume fab already under construction - Expansion and modernization of our Manassas, Virginia facility - Plans to bring advanced HBM packaging capabilities to the U.S. - A $50 billion investment in domestic R&D - Continued progress toward our planned megafab in New York These initiatives are expected to create around 90,000 direct and indirect jobs and will help us meet the surging demand for AI-driven innovation. As someone closely involved in our U.S. expansion strategy, I’m incredibly proud of what this means for our communities, our workforce, and the future of American-made memory. This is about more than just scale—it’s about building resilience, driving innovation, and securing leadership in a critical industry. Thank you to our federal, state, and local partners for your support—and to the Micron team, whose dedication makes this possible. Read more about the announcement: https://lnkd.in/gqGUNQRX See the scale of our Idaho construction: https://lnkd.in/g_Cd4FXA

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Almost exactly 3 years ago I was privileged to stand on stage in Santa Clara and announce the first wave of AI for verification. Today we make probably the most exciting announcement since then! Really excited to work with the ChipStack team as we define and develop Agentic AI for IC development together! ~~ We’re excited to announce that ChipStack, a pioneer in agentic AI for chip design and verification, is joining Cadence. ChipStack’s generative AI-driven platform helps accelerate design and verification workflows through deep design understanding, intelligent test planning, test generation, and AI-assisted debugging. Why this matters for our customers: ✅ Accelerated Verification – Move from weeks to days for front end IC design. ✅ AI-Powered Productivity – Scale without proportional headcount. ✅ Unified Flow – ChipStack’s generative AI agents will integrate seamlessly into Cadence’s Agentic AI and EDA solutions. ChipStack brings deep expertise in AI-driven design understanding, intelligent test planning, and AI-assisted debugging—strengthening our commitment to innovation and time-to-market acceleration. 👉 Read blog: https://ow.ly/NX2E50XpxZI #ChipStack #AI #Semiconductor #Design #Verification

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Intel's new CEO, Lip-Bu Tan, faces the daunting task of revitalizing a company that has recently struggled, lagging behind competitors in key areas like AI. While Tan's track record at Cadence Design Systems inspires optimism, his initial tenure is expected to involve significant restructuring, potentially including layoffs, as he aims to reposition Intel's Integrated Foundry Services (IFS) as a leading semiconductor player. He has affirmed his commitment to IFS, dismissing spin-off rumors, and intends to leverage his market expertise, particularly in China, to capitalize on the booming AI sector. Tan's strategy includes accelerating Intel's 18A chip manufacturing process to attract foundry clients and directly compete with TSMC. While he maintains a strong relationship with TSMC, hinting at potential outsourcing to bridge immediate gaps, his primary focus remains on bolstering Intel's in-house foundry capabilities. The success of this ambitious transition, described by Tan as a "pivotal moment" in Intel's history, will determine whether the company enters a new era of dominance or faces further decline, leaving the board of directors with little room for excuses regarding future performance. #Intel #TechGiants #IntelFoundry #LipBuTan #Chips #Semiconductor #Semiconductors #SemiconductorIndustry #Technology #AI #ChipManufacturing #IFS #TSMC #Leadership #BusinessStrategy #Innovation #SiliconValley #TechNews #Foundry

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As India’s R&D hubs scale at an unprecedented pace, we’re seeing a paradox unfold: greater innovation accompanied by rising burnout. In high-growth settings, it’s easy to get caught in the rhythm of rapid output and short-term wins. But the real breakthroughs in semiconductors, IoT, and wireless connectivity demand focus, patience, and long-view thinking. At Silicon Labs, we’ve institutionalized Quiet Weeks: dedicated company-wide time to minimize distractions, recalibrate, and engage in meaningful problem-solving. It’s not a perk, it’s a principle. One that acknowledges the cognitive rigor of engineering and fosters sustained innovation. This shift makes space for deeper thinking, more intentional collaboration, and gives early-career engineers the freedom to approach challenges expansively, not just reactively. Because in the race to build the future, it’s not about moving the fastest, it’s about thinking the deepest. #InnovationIndia #TechLeadership #LifeAtSiliconLabs

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The most underrated debug technique in RTL? Writing assertions for your own assumptions. They have saved me from so many subtle logic bugs that would have taken hours to trace. If something must be true for your design to work, assert it.

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Hiring patterns changed. RAM prices explained. Hiring strategy across semiconductor companies has quietly shifted. 1. Less generic VLSI hiring 2. More demand for HBM & memory architecture experts 3. High-speed interfaces & advanced packaging 4. Bandwidth, power, and performance specialists That was the first signal. Then came my deductions AI doesn’t just need compute — it needs memory bandwidth. So memory companies shifted capacity from commercial DRAM to HBM for data centers and AI accelerators. What followed was inevitable: Less commercial RAM supply Same demand Higher prices everywhere This isn’t inflation. This is AI-driven prioritization. Your laptop RAM is now competing with AI data centers. And AI always wins. Strategic shift by memory vendors Slowing consumer & commercial DRAM Aggressively pushing HBM for AI & data centers Fewer wafers for PCs, phones, laptops More capacity reserved for high-margin HBM stacks Result? Even regular RAM feels expensive. Hiring patterns tell the future before prices do. Watching how the HBM ecosystem evolves across memory, foundry, and AI platforms. SK hynix / Samsung Electronics / Micron Technology / NVIDIA / AMD / Intel Corporation / TSMC / Amkor Technology, Inc. / ASE Global 💬 Curious to hear from memory, SoC, and system architects — Is HBM the biggest silent disruptor of this decade?

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Everyone thinks Qualcomm is locked into TSMC for 2nm. But Qualcomm is quietly reopening the Samsung Electronics door. Everyone assumes Qualcomm will stay exclusive with TSMC at 2nm. But Qualcomm is now talking to Samsung again. That alone changes the 2nm conversation. This isn’t about nostalgia. It’s about leverage, risk, and capacity in a tightening advanced-node race. Qualcomm learned hard lessons in 2022 with Samsung-built Snapdragon 8 Gen 1. But the market context has changed. At 2nm, dependence on a single foundry is a strategic risk, not a preference. BREAKDOWN • 2nm is the chokepoint → Only two foundries can realistically compete at scale. • Samsung needs an anchor customer → Qualcomm would validate years of foundry reinvestment. • Qualcomm needs optionality → Dual sourcing reduces yield, cost, and geopolitical exposure. Tesla’s recent AI chip deal with Samsung strengthens confidence in Samsung’s advanced-node roadmap. That matters when decisions are made years before volume production. The key question isn’t if Qualcomm trusts Samsung again. It’s how much capacity Qualcomm wants to keep off one island. Is Qualcomm preparing a true dual-sourcing 2nm strategy, or testing Samsung as leverage against TSMC? #Semiconductor #Foundry #2nm #SupplyChain #Geopolitics #AdvancedNodes #ChipManufacturing

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AI isn’t slowing down, and Broadcom continues expanding its optical interconnect solutions portfolio for next-gen AI infrastructure. Today, we’re proud to announce the expansion of our industry-leading 200G/lane DSP PHY portfolio with the introduction of Sian3 and Sian2M, purpose-built for the demanding connectivity requirements of AI/ML clusters. Learn more: https://dy.si/HM9MHj2

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𝐓𝐨𝐝𝐚𝐲 𝐦𝐚𝐫𝐤𝐬 𝐭𝐡𝐞 𝟏𝟎𝐭𝐡 𝐚𝐧𝐧𝐢𝐯𝐞𝐫𝐬𝐚𝐫𝐲 𝐨𝐟 𝐀𝐧𝐬𝐲𝐬' 𝐚𝐜𝐪𝐮𝐢𝐬𝐢𝐭𝐢𝐨𝐧 𝐨𝐟 𝐆𝐞𝐚𝐫 𝐃𝐞𝐬𝐢𝐠𝐧 𝐀𝐮𝐭𝐨𝐦𝐚𝐭𝐢𝐨𝐧! This acquisition stands out as one of the most successful in the EDA industry. The magic started with a small team of 10 people who revolutionized how chip design signoff is performed. Gear was a pioneer, introducing SeaScape - the first purpose-built Big-Data platform for EDA. SeaScape also popularized the use of Pythonic APIs in EDA at scale, a major industry shift! Ansys made a bold move by completely rewriting all its EDA tools on the new SeaScape platform, without reusing a single line of code. This led to the resounding success of tools like RedHawk-SC, Totem-SC, and PathFinder-SC, which enabled customers to perform signoff analysis on chips with trillions of transistors. Ansys successfully migrated its entire customer base to SeaScape, added hundreds of new customers, and even displaced competitors at several accounts. Super proud to have been a part of the team that pioneered this revolution. A huge thank you to all our customers and partners for making this journey so successful! #Ansys #GearDesignAutomation #EDA #Semiconductor #SeaScape #Anniversary #Innovation #BigData #Python RamaRao ( Vishal ) Nemalikanti Calvin Chow Emmanuel Blanc Ehud Tamar Anant Narain Nayan Chandak Vinayakam Subramanian Sankar Ramachandran Mithun Rao Dileesh Jostin Teong-Ming Cheah Ted Chan heesung Choi Masaya Takahashi Murat Becer Preeti Gupta Marc Swinnen

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Cerebrus vs. Innovus: How AI is Transforming VLSI Physical Design In the world of VLSI, physical implementation tools shape the backbone of innovation. For years, Cadence Innovus has been the go-to for digital place-and-route, enabling engineers to optimize power, performance, and area (PPA). But as SoCs scale in complexity, and time-to-market pressures intensify, classical flows face bottlenecks. Enter Cadence Cerebrus, an AI-driven powerhouse redefining physical design by wrapping intelligence around the entire Cadence digital implementation suite (Genus, Innovus, Tempus, etc.). 🆚 Innovus vs. Cerebrus: Key Differences Optimization: Innovus — Manual, user-driven Cerebrus — AI-guided, automated Design Space: Innovus — Limited sweeps Cerebrus — Massive, AI-optimized Learning: Innovus — None Cerebrus — Reinforcement learning Scalability: Innovus — Multithreaded Cerebrus — Cloud-native, distributed Results: Innovus — Good (user-dependent) Cerebrus — 5–20% better, faster Engineer’s Role: Innovus — Iterative tuning Cerebrus — Goal-setting, innovation ⚙️ Cerebrus Highlights 🔹 Reinforcement Learning: Continuously learns which flow options yield the best PPA. 🔹 Massive Parallelism: Runs 100s–1000s of scenarios concurrently. 🔹 Scenario-Based Exploration: Define floorplans, constraints, or frequencies. Cerebrus ranks outcomes by cost functions (timing, area, power). 🔹 Meta-Learning: Applies past learnings to new blocks/projects, accelerating convergence. 🔹 Dynamic Flow Adaptation: Adapts in real time to changes in design or constraints. 🔹 Interactive Dashboards: Visualize trends, improvements, and next steps. 🛠 Workflow Snapshot Traditional Innovus (TCL-based): tclCopyEditread_sdc constraints.sdc   floorPlan ...   place_opt   clock_opt   route_opt   report_timing   # Iterate manually Cerebrus AI Flow: Define YAML/JSON scenario Set targets: freq: 2.5GHz, min_area: true Launch with launch_cerebrus_flow Cerebrus autonomously explores and optimizes 🚀 Real-World Impact ✅ Speed: Reduces design closure from months to days ✅ Results: Up to 20% better timing/area/power ✅ Scalability: Perfect for billion-transistor SoCs ✅ Productivity: Engineers focus on design, not iterations 🔍 Why This Matters for Indian VLSI Engineers Cerebrus isn’t just another tool; it’s a paradigm shift. As India ramps up chip design efforts, adopting AI-driven flows is critical to stay competitive globally. Companies using Cerebrus are breaking the limitations of human tuning and achieving better silicon faster. If you're building the chips of tomorrow, Cerebrus is the leap beyond Innovus you've been waiting for. #VLSI #Cadence #Cerebrus #Innovus #Semiconductors #ChipDesign #PhysicalDesign #EDA #AIinVLSI #PPA #SoC #IndianSemiconductor #ReinforcementLearning #TechTrends #EDAtools

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