John Kaminski

Have you thought about various DSP architectures in high-performance computing applications? This week's blog topic centers on use cases for Digital Signal Processing (DSP) to maximize processing efficiencies. https://lnkd.in/gypE9uU5

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Think of an FPGA as a Swiss Army Knife. It’s the ultimate tool for the Unknown. When 6G standards are still shifting and protocols are evolving in-orbit, you need the ability to reconfigure your "blade" on the fly. It’s hired muscle that can learn new tricks. But when you hit scale, flexibility becomes a Tax. An ASIC is the surgical scalpel. It does exactly one thing, but it does it with 10x the power efficiency and 100x the speed. In a Satcom world where every mW of thermal load matters, the scalpel wins. The most expensive mistake isn't picking the wrong chip, it's staying with the "Knife" when the mission requires the "Scalpel." Knowing when to harden your logic is the difference between a prototype and a product. #RFEngineering #ASICDesign #FPGADevelopment #Semiconductors #EmbeddedSystems

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We're excited to share the Vol. 72, Issue 6 TCAS-II paper highlight, “A 22.5∼28.5-GHz Low-Amplitude-Variation Low-Phase-Error Hybrid Phase Shifter Using Flatness Enhancement Techniques for 5G NR in 40-nm CMOS." 📝 Authored by: Shiping Zheng, Yun Wang, Ziyang Deng, Chen Jiang, Hongtao Xu This brief presents a hybrid phase shifter (PS) that integrates a three-stage switch-type phase shifter (STPS) and a one-stage reflect-type phase shifter (RTPS). The STPS utilizes a flatness-enhanced π -network topology to reduce phase error and insertion loss (IL) variation by eliminating feedback and resonant capacitors. 🔗 Continue reading here: https://loom.ly/5GrI2ZU #IEEE #IEEEPublications #CircuitsandSystems #ResearchBriefs #TCASII

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🚀 As the first to request LTE-M tools in SignalPro, Ubiik are thrilled to see a dedicated NB-IoT/LTE-M module in EDX Wireless come to life as a powerful enhancement to their software. "We’re thrilled to support Ubiik’s mission of enabling scalable and standards-based wireless infrastructure for smart utilities." — Anoop Kaur Bowdery CEO, EDX Wireless “EDX SignalPro enables Ubiik to efficiently optimize large-scale designs while offering customers a simple way to visualize coverage. We look forward to using it to improve deployment strategies in upcoming projects.” — Mark Fecci VP of Sales, U.S., Ubiik 🔍 Discover how Ubiik is delivering smarter networks for utilities and IoT ecosystems : https://lnkd.in/gEEf4uUi #Ubiik #EDXwireless #SignalPro #PrivateLTE #AMI #SmartGrid #Utilities #IoT #Connectivity

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M31 Technology Advances AIoT Innovation with Ultra Low Power Memory Compilers on TSMC N6e Platform https://lnkd.in/eUxqBfkc Developed on TSMC’s advanced N6e platform, these compilers are optimized for ultra-low power consumption to meet the stringent requirements of AI-driven edge and IoT devices. Read more at https://lnkd.in/eUxqBfkc #semiIP #IPcores #semiconductor

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SimpleChips invites all power engineers to stop by its booth (2218) at #APEC2026 in San Antonio from March 23rd to 25th. SimpleChips will be promoting its 1200V monolithic high-voltage monitor IC (<0.7% accuracy) along with its ASIC manufacturing capabilities. Every "river walk" leads to SimpleChips!

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⚡ #UNITips | Why Bandwidth Matters ⚡ Limited oscilloscope bandwidth can: 1️⃣Round off fast edges 2️⃣Miss narrow glitches 3️⃣Distort signal integrity That’s why engineers need higher bandwidth for today’s high-speed designs. The new UNI-T MSO8000HD offers up to 8 GHz bandwidth, 20 GSa/s sampling, and 12-bit resolution, giving you the clarity and confidence to measure what really matters. Learn more➡️https://lnkd.in/gGwtXW_6 #Oscilloscope #SignalIntegrity #HighSpeedDesign #UNITREND

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Achieving high Q factor is essential for minimizing insertion loss in RF and microwave components. Watch this short video to learn some of the techniques we use to achieve a high Q factor and superior RF performance.

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Now available on-demand! Why is differential signaling more robust than single-ended? Prof. Eric Bogatin explores how differential signaling resists ground-plane noise and how to measure signal integrity issues in your PCB designs. Free to watch– get started here: https://lcry.us/46arHPA #pcbdesign #testandmeasurement #teledynelecroy

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At Pure Silicon, our engineers push #verification forward through curiosity, collaboration, and a commitment to continuous learning. Today we’re pleased to spotlight Sasa Stamenkovic, Principal Engineer, Formal Verification, whose work in #formalverification and #abstraction techniques helps our customers navigate complex design challenges with clarity and confidence. Get to know him in this Q&A: 1. What’s your current focus area at Pure Silicon, and what types of projects or developing technologies are you most excited about right now? My focus right now is on strengthening relationships with customers and building the kind of long-term engagements where both sides can succeed. Over the past six months, I’ve dedicated most of my time to practicing formal property verification (#FPV) and sharpening my skills in various adoption and abstraction techniques. What excites me most is the growing role of #machinelearning in formal verification. There is enormous potential for ML to take on some of the more time-consuming and error-prone tasks—like breaking down specifications or generating repetitive code—so #engineers can focus on deeper problem-solving instead of boilerplate. 2. What’s one #engineering challenge you’ve solved recently that you’re especially proud of? At the most recent Cadence JUG conference, I had the opportunity to suggest using initial value abstraction (IVA) to address the #convergence problem a presenter was facing. It wasn’t a technique that had been considered for their specific scenario, but it fit the challenge remarkably well. Contributing a solution that helped reframe the problem—and potentially unblock their verification flow—was especially rewarding. 3. How do you see #chipdesign or #verification evolving over the next few years? I expect adoption of formal verification to continue growing, both at the IP level and across more complex system contexts. Despite the rise of AI-assisted tools, I don’t believe engineers will be replaced. Instead, AI will become a powerful assistant, helping automate tedious steps while engineers continue to guide strategy, abstraction, and interpretation. 4. What’s one tool, method, or mindset that you think gives engineers an edge in tackling complex #SoC or IP verification problems? A mindset I value highly is “one team, one goal.” No single engineer can solve every problem alone, and a second set of eyes often reveals patterns or issues you might miss when you’re too deep in the details. Collaboration brings clarity, speed, and better outcomes. 5. When you’re not deep in waveforms or code, what do you enjoy doing outside of work? Outside of engineering, I love spending time with my wife and our children. That time together is grounding and reminds me why I enjoy the work I do.

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**Most DV engineers hit a wall after three years.** If you’re still tweaking the same test‑bench you wrote in your first job, you’re already falling behind. In digital verification the toolbox looks small—SystemVerilog, UVM, a few simulators—but the real differentiator is **architecting verification strategies that scale with silicon complexity**. 🔎 **Industry reality:** ≈ 70 % of engineers at the 2‑3‑year mark are still “test writers.” The remaining 30 % have become verification leads because they stopped asking *“How do I write this test?”* and started asking *“How do I prove this block is bug‑free with minimal regression cycles?”* ### The 3‑Step DV Growth Framework 1. **Depth → Breadth** – Own one methodology (UVM) end‑to‑end, then apply it to a different IP. Cross‑domain work forces system‑level thinking. 2. **Metrics‑Driven Ownership** – Move from “the test passed” to “I own coverage closure, bug‑escape rate, and regression time.” Let hard data define your impact. 3. **Leadership Through Automation** – Build reusable UVCs, scoreboards, and checkers and embed them in a CI pipeline. Automating the routine 80 % makes you the 20 % that shapes architecture. **Contrarian view:** Specializing in a single tool is a dead‑end. New simulators and formal engines appear daily; the only lasting advantage is a strategic mindset—evaluating, integrating, and evolving verification flows faster than the competition. **Takeaway:** If you’re still counting test cases, you’re counting yourself out. Pivot to metrics, own the end‑to‑end flow, and let automation be your lever. The next three years will either make you a verification leader or consign you to the background noise of the silicon floor. Choose wisely.

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Blog: "Introducing Cadence's Virtuoso Studio #RF: Advancing RF Design for 3D-IC" https://lnkd.in/ecJsCnBc Next-generation RF to millimeter-wave silicon MMIC and module product development software Read more at https://lnkd.in/ecJsCnBc #chiplet #3DIC #AdvancedPackaging #MultiDie #semiconductor #semiEDA

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With the growing need for high-speed internet and broadband connectivity in underserved and rural areas, #NTN deployment becomes more important. But this brings new validation challenges for engineers designing chipsets, devices, and modules. Read this Microwaves & RF article to learn how to address them with a proper test environment: https://bit.ly/48YRr2f

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Read about built-in temperature and load sensors for GaN power amplifiers in the March 2026 issue of IEEE Microwave Magazine! "Sensors for III-V Power Amplifiers" by Grace Gomez, Devon T. Donahue, and Taylor Barton This article presents an overview for the development of GaN and other III-V PAs with built-in temperature and load sensing to monitor reliability and performance factors.   To read more, go to https://lnkd.in/eERz_3jb #MicrowaveTechnology #Innovation #MicrowaveMagazine #IEEEMicrowaveMagazine #MicrowaveEngineering #FebruaryIssue #MHztoTHzCommunity #PowerAmplifier #GaN #GaNPA #PA

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Introduced in 1974, the TMS1000 family from Texas Instruments combined CPU, ROM, RAM, and I/O on a single die and established the commercial template for the microcontroller. https://lnkd.in/g6NCkcHF

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