New Wave Design

The intended outcome is clear. The hardware requirement isn't, because a specific technical problem has to be solved before anyone can write it. That phase gets underestimated every time. It looks like a short detour. It rarely is. The blockers that hold up defense programs early tend to sit at the intersection of hardware, firmware, and system integration - where neither the hardware engineer nor the firmware engineer can resolve them alone. When outside technical depth steps in during the investigation phase. before the requirement is locked, the diagnostic compresses. The requirement gets written with the benefit of what was learned. Hardware selection is better-informed. The development phase starts with more margin. Early technical engagement isn't common practice. It should be. Read it here: https://lnkd.in/g7qxAFme

We hear Mr. @Tolleson's call! New Wave Design is committed to rapid prototyping and speed to capability for the Warfighter. Contact our team today to discuss your prototyping effort, let us solve your most challenging rugged processing and high speed protocol problems. www.newwavedesign.com

Some requirements don't have a catalog answer. The bandwidth is too high. The form factor doesn't exist. The interface combination is specific enough that no COTS vendor has built it. Custom hardware development is the only path. And in defense, that path has a well-documented history of schedule overruns. Most of that risk concentrates in the same place: the boundaries between hardware, firmware, and software - where assumptions made by different teams don't survive contact with each other. When one team owns architecture, board design, FPGA firmware, and software drivers together, those boundaries become internal problems instead of vendor coordination failures. Debug cycles happen faster. Integration surprises happen earlier, when there's still margin to absorb them. The decisions that most affect schedule are made in the first few weeks, before the architecture is locked. This week's post covers what full-stack custom FPGA hardware development actually requires on a defense program. Read it here: https://lnkd.in/gHXjwFQg #FPGA #CustomHardware #DefenseEngineering #EmbeddedComputing #MilAero #3UVPX #HPEC #AMDVersal #FPGADevelopment #DefensePrograms

The requirement is defined. The architecture is scoped. The hardware is selected. And the program is sitting still because the internal team doesn't have the bandwidth or the specific FPGA depth this phase requires. Hiring takes months. The program doesn't have months. The FPGA engineering talent shortage is a current program constraint, not a future concern. VHDL and Verilog fluency, Versal toolchain experience, PCIe driver development - narrow skills that take years to build and are in demand everywhere at once. Directed engineering resources fill that gap without adding permanent headcount. Engineers working under the program's own technical leadership within its own structure, not a separate workstream running in the background. The oversight stays intact. The work moves. This week's post covers how to think about bandwidth gaps vs. skills gaps, and what directed resources actually look like in practice. Read it here: https://lnkd.in/gNgCB9vW #FPGAEngineering #DefensePrograms #StaffAugmentation #FPGA #MilAero #EmbeddedComputing #VHDLVerilog #AMDVersal #SystemsEngineering

New Wave is adding a Senior Sales Associate to grow our presence on the East Coast.   We’re looking for someone who can navigate complex sales cycles, build strong customer relationships, and translate technical value into business impact.   If you’re ready to help shape what’s next at New Wave apply now: https://lnkd.in/gMpVWBpf   #Hiring #Sales #TechCareers

It's a busy week for New Wave Design - some of our team members are at AMD's #SPWG event in Colorado to discuss the mapping of high-performance signal processing applications on AMD Versal™ Adaptive SoC devices. If you're in the area, stop by to chat with our team! #AMD #SPWG #Versal #DigitalSignalProcessing

Heading to #NIConnect? Stop by booth K114 to hear about our new products and chat with our team!

The platform isn't getting replaced. The legacy bus isn't getting re-architected. Still, the upgrade requirement is real and the new COTS hardware doesn't speak the same protocol. That mismatch is exactly where platform upgrades stall. FPGA-based protocol bridging is how programs close that gap without touching the legacy side. The bridge sits between the new hardware and the existing platform bus, translating bidirectionally at line rate, deterministic, transparent to both sides. Fibre Channel to Ethernet. ARINC-818 to Ethernet. HSDB to Ethernet. Each one built from verified protocol IP on production-qualified hardware. The NRE scope is narrower than it looks, and the path to a qualified deliverable is shorter than starting from scratch. If your program has a legacy interface requirement that doesn't map to what's in any catalog, this week's post is worth the read. Read it here: https://lnkd.in/geuQ_jmz #FPGA #ProtocolBridging #DefenseElectronics #LegacyInterface #3UVPX #ARINC818 #FibreChannel #MilAero #EmbeddedComputing #COTSHardware

The FPGA vs. GPGPU debate is the wrong question for most modern defense programs. EW, SAR, COMINT, autonomous navigation — none of these mission sets require one type of processing. They require all three simultaneously: deterministic front-end signal acquisition, high-throughput AI inference, and control logic. Separate boards for each creates integration complexity and backplane pressure that SOSA-aligned 3U VPX systems can't absorb. Adaptive SoCs resolve that. FPGA for the sensor front end. AI Engines for the parallel math. ARM for decision logic and networking. One chip. No inter-chip bottleneck. The USAF's shift to MOSA and SOSA standardized the hardware interfaces that make this practical — so a new AI algorithm can reach the fleet in weeks, not after the next hardware refresh. Not FPGA or GPGPU. Heterogeneous computing built for the speed of the threat. Read it here: https://lnkd.in/gqDGT-Qp #MOSA #SOSA #AdaptiveSoC #HeterogeneousComputing #3UVPX #DefenseElectronics #AMDVersal #FPGA #OpenArchitecture #MilAero

In electronic warfare, the question isn't whether you detected the threat. It's whether you responded before the threat mattered. GPGPUs can't make that guarantee. An OS driver, a memory hierarchy, a scheduling cycle — any of it introduces jitter. In EW, a few hundred nanoseconds of jitter is the difference between jamming a radar pulse and missing it entirely. FPGAs can make that guarantee. The logic is a physical circuit. 450 nanoseconds means 450 nanoseconds — every time, at temperature, in the field. What Adaptive SoCs changed is that determinism at the front end no longer requires giving up AI capability at the back end. FPGA fabric handles the Sense-Identify-Act loop. AI Engines classify agile emitters alongside it. The system stops being a reactive jammer. It becomes an intelligent sensor. This week's post covers how FPGA vs. GPGPU latency plays out in real EW and DSP applications — and why the front-end determinism question is non-negotiable. Read it here: https://lnkd.in/gwuVxfQ2 #ElectronicWarfare #FPGA #EW #DSP #SOSA #AdaptiveSoC #AMDVersal #SIGINT #DefenseElectronics #CognitiveEW