Harshad Junnarkar

🚗 No Room for Error: How OCXOs Guide Autonomous Vehicles When a vehicle drives itself, timing isn’t just critical—it’s everything. Behind every safe lane change, smooth stop, and real-time decision lies an unsung hero: the Oven-Controlled Crystal Oscillator (OCXO). Here’s how OCXOs enable autonomy: 📍 Precise Sensor Sync – Coordinates LiDAR, cameras & radar with microsecond accuracy 🌡️ Temperature Resilient – Stable performance from freezing mornings to hot asphalt 📡 GNSS Reliability – Enhances GPS accuracy for exact positioning 📊 Clean Signal Integrity – Low phase noise ensures trustworthy navigation data Where OCXOs Drive Impact: • Sensor fusion for 360° awareness • Real-time path planning & obstacle avoidance • Vehicle-to-everything (V2X) communication At Dynamic Engineers, we engineer the timing solutions that help autonomous vehicles navigate our world with confidence—because on the road to autonomy, every nanosecond matters. #AutonomousVehicles #OCXO #AdvancedDriving #SensorFusion #SmartMobility #EmbeddedSystems #DynamicEngineers #Innovation #EverythingRF

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Electrification and rapid innovation in ADAS and in-vehicle features have transformed the car into a dynamic, software-defined machine. I spoke with EE Times | Electronic Engineering Times about this profound shift - and how Arm is playing an instrumental role in powering the enhanced features drivers have come to expect. From enabling high-performance, power-efficient compute to leading industry collaboration through SOAFEE, we're accelerating the journey to software-defined vehicles and delivering cloud-to-car parity to make this technology scalable and capable of real-time improvements. https://lnkd.in/g49q23XK

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The electric vehicle industry is advancing quickly, yet optimizing battery health, charging efficiency, and cost remains essential for widespread adoption. In a conversation during #FTCar, ADI’s Roger Keen shares how innovation and collaboration are shaping the road to a more resilient EV future:

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Big news from Micron today—this marks a pivotal moment in our mission to advance U.S. semiconductor leadership. We’re expanding our U.S. investments to approximately $200 billion, reinforcing our long-term commitment to domestic memory manufacturing and R&D. This includes: - A second leading-edge memory fab in Boise, Idaho—complementing the high-volume fab already under construction - Expansion and modernization of our Manassas, Virginia facility - Plans to bring advanced HBM packaging capabilities to the U.S. - A $50 billion investment in domestic R&D - Continued progress toward our planned megafab in New York These initiatives are expected to create around 90,000 direct and indirect jobs and will help us meet the surging demand for AI-driven innovation. As someone closely involved in our U.S. expansion strategy, I’m incredibly proud of what this means for our communities, our workforce, and the future of American-made memory. This is about more than just scale—it’s about building resilience, driving innovation, and securing leadership in a critical industry. Thank you to our federal, state, and local partners for your support—and to the Micron team, whose dedication makes this possible. Read more about the announcement: https://lnkd.in/gqGUNQRX See the scale of our Idaho construction: https://lnkd.in/g_Cd4FXA

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Secrets of Successful Full Chip XTalk ECOs   Quick recap for PD and STA engineers  XTalk ECOs usually hit when the design is almost frozen and SI on STA suddenly turns a clean chip into a problem. In deep sub micron SoCs, coupling heavy interconnect can flip a small positive margin into a violation once you move from block level to full chip.  Why it hurts at full chip  - Block clean is not equal to chip clean. At top level, timing windows change, new aggressors appear, and marginal paths fail when SI is enabled.   - SI off versus SI on gap. Long buses and macro channels pick up large delta delays and noise glitches that never showed up in non SI runs.   - Time pressure. Full chip SI STA across corners is slow, so random ECOs and trial and error can easily waste days.  How the tool really sees XTalk  SI STA loads coupled SPEF, builds early and late arrival windows, finds overlapping aggressors, and computes two key effects:  - XTalk delay: extra delta delay on victims that can dominate cell delay on long coupled nets.   - XTalk noise: glitches on quiet nets compared against library noise immunity limits.  A net is risky when it is highly coupled and its timing window overlaps with many neighbors.  A practical 5 step flow   1. Baseline SI setup-Coupled parasitics loaded, SI delay and noise enabled on key corners, reports and slack sanity checked. 2. First SI on sweep-Run full chip SI STA, dump timing with delta delay breakdown and noise reports for worst nets and endpoints.   3. Cluster, do not chase one by one-Group violations into patterns like long buses, dense hotspots, macro channel routes, and noise only control or reset nets.   4. Targeted fixes per pattern-Long buses: move to higher metals, add spacing, add shields. Hotspots and channels: tighten routing constraints and relieve congestion. Interfaces: use SI aware ILMs and clean boundary routes. Noise only: strengthen victims, upsize drivers where safe, add guard nets. 5. Incremental iterate-Reextract changed regions, rerun SI on critical corners, then stop when SI on margins and noise limits meet your signoff bar.  ECO tricks that usually work   - Prefer routing fixes like spacing, shielding and layer promotion over blind buffer drops.   - Use buffers to split very long victims and shift timing windows, but always check setup and hold and watch for new aggressors.   - Upsize carefully. Stronger victims see less noise, but stronger aggressors can hurt nearby nets and increase IR and EM stress.   - SI on STA shows no unwaived setup or hold violations on required signoff corners.   - Noise checks show peaks and widths within limits on sensitive nets like resets, enables and clock gating controls.   - No single net contributes large XTalk delta delay to many critical paths without a clear mitigation or waiver.  If you treat XTalk critical, cluster violations, automate, and no random net fixes, FC SI ECOs become tough but predictable instead of a last minute tapeout shock.

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The new standard in automotive charging: Featuring a secure, multi-core design with Qi2 support and FOTA capabilities, WCT-15WAUTOS2 powers next-gen in-vehicle wireless experiences. https://lnkd.in/eiazKtGb

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Cut over 90% of your costly ADAS/AD simulations without missing critical edge cases. Tempero’s AI-driven verification suite identifies the needle in the haystack of your scenario space. In one example, focusing on the most complex scenario in UN Regulation No. 157 (ALKS): - Over 1 million generated simulation scenarios - More than 40,000 valid scenarios - Only 2 critical safety cases, representing just 0.005% of the valid configuration space. When comparing: - Traditional full-coverage: over 40,000 simulations - Tempero fuzzing suite: only 2,434 simulations This results in a 94% reduction in compute, cloud, and simulator licensing costs, saving energy and accelerating safety validation. Fewer runs, faster insights, and lower costs lead to smarter safety verification for the Software-Defined Vehicle era. Interested in seeing how this applies to your own simulation stack? Let’s talk. #ADAS #Verification #Simulation #Safety #SoftwareDefinedVehicles #Fuzzing #AI #Tempero

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Automakers are scaling ADAS across vehicle tiers using Qualcomm’s Snapdragon Ride platform. The architecture supports cockpit integration, safety-certified software, and real-world validation across 60+ countries and 300M+ miles. More than 20 OEMs have announced programs using Snapdragon Ride, including deployments in mass-market vehicles via the Ride Flex SoC. Learn more about the architecture, scalability, and validation metrics behind Snapdragon Ride: https://bit.ly/4oxRAiX

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One compute box. Multiple displays. A cockpit experience built for clarity at speed. At CES 2026, we showcased the cockpit compute system featured in the Mahindra Electric Origin SUVs XEV 9e. Multiple displays run from a single compute box, and 5G connectivity on the same box supports a fast UI with seamless handoffs across screens. Media, navigation, and vehicle information stay in one connected view. Why does this matter? When compute and connectivity are designed together, the cabin feels calmer and more intuitive. Drivers spend less time hunting for information and more time focused on the road. This demo was part of a broader pavilion lineup focused on the in-vehicle experience and software-defined capabilities. Want to build the technology behind experiences like this? Explore opportunities at https://bit.ly/4ryIsvl #AptivCES2026 #SoftwareDefinedVehicle #InVehicleExperience #AutomotiveTech #CockpitCompute

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In ASIC design, good specifications are not optional. They are the first layer of safety. Those of us working in automotive and other safety-critical domains know this deeply. A missing requirement or an ambiguous line in a spec is not just a process issue. It can cascade into design bugs that ultimately put real people at risk. What’s interesting is how the rise of LLMs highlights this truth in a new way. These tools are incredibly powerful, but only when they are given crystal clear instructions. If you give them vague direction, you get vague output. If you give them precision, you get productivity. It’s a mirror of our own engineering discipline. Clear inputs lead to safe and reliable outcomes. This new reality is going to reshape the way all white-collar work is done. The ability to define crisp specifications, describe tasks unambiguously and express intent with clarity is becoming a core skill, not a niche one. In a way, LLMs are teaching us a lesson we already knew: quality starts with clarity.

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Almost exactly 3 years ago I was privileged to stand on stage in Santa Clara and announce the first wave of AI for verification. Today we make probably the most exciting announcement since then! Really excited to work with the ChipStack team as we define and develop Agentic AI for IC development together! ~~ We’re excited to announce that ChipStack, a pioneer in agentic AI for chip design and verification, is joining Cadence. ChipStack’s generative AI-driven platform helps accelerate design and verification workflows through deep design understanding, intelligent test planning, test generation, and AI-assisted debugging. Why this matters for our customers: ✅ Accelerated Verification – Move from weeks to days for front end IC design. ✅ AI-Powered Productivity – Scale without proportional headcount. ✅ Unified Flow – ChipStack’s generative AI agents will integrate seamlessly into Cadence’s Agentic AI and EDA solutions. ChipStack brings deep expertise in AI-driven design understanding, intelligent test planning, and AI-assisted debugging—strengthening our commitment to innovation and time-to-market acceleration. 👉 Read blog: https://ow.ly/NX2E50XpxZI #ChipStack #AI #Semiconductor #Design #Verification

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