Aditi Kulkarni

📺 Ever wondered where PWM or PDM is actually used in real life? Most of us remember learning about modulation techniques like PWM (Pulse Width Modulation) or PDM (Pulse Density Modulation) in our embedded systems classes... ...and then we forgot them. Not because they’re useless, but because no one told us where they really shine. 🎯 One underrated yet daily use-case? Your TV or AC Remote. Yes, seriously. Every time you press a button to change the channel or switch off the AC, you're unknowingly triggering a PWM-based communication. 🔍 So How It Works: Infrared (IR) remotes use modulation techniques like PWM or PDM to encode data into light pulses. ➡️ Each key on your remote corresponds to a unique code ➡️That code is sent using bursts of IR light, modulated with PWM ➡️The receiver decodes the duration and gaps between pulses to figure out the command This is how your TV knows you pressed volume up, not power off. ⚙️ Why PWM? Resistant to noise Easy to implement in hardware Efficient for short-range line-of-sight communication 🤯 You thought PWM was only for motor control? Turns out — it’s literally in your hand, every time you use your remote. 💬 So next time you press a button on your remote… Remember: you’re not just flipping channels. You’re engaging a classic embedded system concept — in action! #EmbeddedSystems #microcontroller #programming #C #Cprogramming #SignalProcessing #TechFacts #Electronics

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*** Changing Role of Verification Engineers in a Chiplet World *** In a monolithic SoC world, a verification engineer’s job was mostly: o Ensuring functional correctness of individual IP blocks. o Running full-chip verification across a single die. o Debugging issues inside the same physical domain. But in a chiplet-based SoC, the role expands: o Understanding inter-chiplet protocols and system-wide behavior. o Modeling interactions across dies, not just within a single die. o Debugging failures where the root cause might be in the package, not just the chiplets themselves. Chiplet-based SoCs blur the lines between: o Digital and physical verification—since interconnect and package-level effects are inseparable. o Pre-silicon and post-silicon validation—because real-world behavior isn’t always captured in traditional simulations. o Design and verification responsibilities—since partitioning choices impact how easily a system can be tested. Verification is no longer just about "checking correctness"—it’s about understanding the full system at every level. How do we train the next generation of verification engineers for this shift?

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*** Silent Killer in High-Speed Interface Design *** Every engineer working on PCIe, USB, CSI, DSI, LPDDR, SerDes, or any high-speed interface knows: "Timing closure will keep you Up at night." But here’s the thing—It is not always the big violations that kill a design. These can be found and fixed. The silent killers are the marginal cases: * That one Async Clock Domain Crossing that looked fine… until Silicon. * That Power mode Transition that only happens under rare Conditions. * That Corner case in Equalization that only fails in a specific voltage/temp combo. "These don’t show up in the standard verification flow. You have to hunt them down." What’s your approach to catching these hidden pitfalls?

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I Spent 12 Years in DFT. Here’s What I Wish I Knew in My First 2 Years In my second year, I thought I had it all figured out. I was validating a complex scan chain. My testbenches looked perfect. The final simulations ran for weeks without errors. I felt confident. Then the first silicon arrived. We powered up the chip. The scan chain failed immediately. After days of debugging, I found the real issue: ⚡ A subtle clock domain crossing bug. ⚡ Not in the code, but in my assumptions. ⚡ I trusted simulations too much. Here’s what I wish I knew back then: ✅ No simulation can replace real hardware understanding. Passing simulations doesn’t guarantee success in silicon. ✅ Always question your assumptions. Ask “what could go wrong” even when all tests pass. ✅ Experience is built by catching the unknowns. Good engineers write code. Great engineers search for the cracks that tools can’t catch. A passing simulation is not the finish line. It’s the starting point for deeper investigation. 👉 What hard lesson shaped your engineering journey? #Semiconductors #DFT #Engineering #LessonsLearned #ChipDesign #stemachip

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For Embedded Engineers considering a move in 2026, a few honest observations from the market. The strongest engineers I speak to are not the ones who know every RTOS or MCU family. They are the ones who can explain why a system was architected a certain way, how they handled failure modes, and what tradeoffs they made under real constraints. What is coming up repeatedly in interviews right now Ownership of firmware architecture, not just feature delivery Clear experience with real hardware bring up and debugging Comfort working cross functionally with EE and Mechanical teams The ability to talk through decisions, not just list tools On the flip side, the best companies are Having engineers interview engineers Keeping technical panels practical, not academic Being clear on impact, scope, and expectations early If you are evaluating opportunities this year, focus less on job titles and more on ownership, decision making, and the problems you will actually be trusted to solve. In the end, the engineers who stand out are the ones trusted with decisions, not just code. #beUneek #EmbeddedEngineers #Embedded

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🧠Interrupts vs Polling in Embedded Systems: ESP32 & STM32 Best Practices When designing real-time embedded systems, one of the most important architectural decisions is: 👉Should you use interrupts or polling? This choice can define your system's latency, power consumption, and scalability-critical factors in IoT development, firmware architecture, and microcontroller design. 🔴Polling in Embedded Systems ✅Easy to implement in firmware ✅Suitable for low-frequency or non-critical tasks ⚠️ Drawback: Consumes CPU cycles, reduces efficiency, and increases power consumption 🔴Interrupts in Embedded Systems ✅Event-driven execution → perfect for real-time responsiveness ✅Widely used in ESP32, STM32, and ARM Cortex-M microcontrollers ✅Critical for UART, SPI, I2C, CAN, and sensor data acquisition ⚠️ Requires careful design: race conditions, interrupt priority, and latency management 🤔My Proven Approach (ESP32 + STM32 Projects): hybrid model in firmware design: 🔹Interrupts high-priority tasks (sensor triggers, data reception, communication protocols) 🔹Polling background processes (system diagnostics, logging, Ul updates) #RaspberryPi #Arduino #EmbeddedSystems #Embedded #loT #ElectronicsEngineering #TechInnovation #ElectronicsProjects #TechEnthusiast #MakersCommunity #STEM #LearningByDoing

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Waveguide combiners are key components for today's small form factor smart eyewear: they are thin, light weight and provide a generous eyebox. 60 years ago, VLSI was a great way to reduce costs for ICs, producing thousands of replicas in a single wafer. This is not the case for AR waveguides, were only a handful can be packed on a single wafer, making wafer scale waveguide fab a risky bet for a consumer device. Moving from wafer scale to plate scale process might change this cost structure, as it did for LCD displays 40 years ago. Join us tomorrow Tuesday 11/18 at 9am PST for an informative SPIE Fireside chat with Morphotonics (NL) to learn about their novel plate processing technology to make diffractive waveguides a realistic option for mainstream consumer smart glasses. Please register ahead of time to be able to view the chat at your convenience. https://lnkd.in/g7MmtEjW #SPIEXR #XR #AR #MR #VR #smartglasses #aiglasses #waveguides #NIL

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🚀 Inside the Analog Mind: How an Inverter Thinks Like an Amplifier! (Post 1 of 2 transistor circuits) Ever looked at a simple CMOS inverter and thought—"This is just a logic gate"? Well, let’s put on our analog designer’s hat and see it in a whole new light! 🌀 The CMOS Inverter – A Hidden Amplifier? (Case 1) Imagine a seesaw. When one side goes up, the other must go down—it’s all about balance. That’s exactly how a CMOS inverter (Case 1) operates. When the input is high, the NMOS transistor turns ON and pulls the output low, while the PMOS is OFF. Flip the input, and the roles reverse. But if you pause and look at it differently, doesn’t this resemble a common-source amplifier? 🔍 Think like an analog designer: The pull-up PMOS and pull-down NMOS aren’t just switches—they form a dynamic active load. The transition between logic states isn’t abrupt—it’s actually an amplification process where the circuit responds to even small input variations before fully switching. If you bias the inverter in its transition region, it starts behaving like a high-gain amplifier. That’s the trick used in sense amplifiers and analog comparators! Now, what happens if you cascade two inverters? It starts resembling a two-stage amplifier, restoring signal strength and rejecting noise. ⚡ The DTMOS Inverter – When the Body Joins the Game! (Case 2) Now let’s supercharge this idea with Case 2: The DTMOS inverter. Here, the body terminal is dynamically connected to the gate, adapting its threshold voltage based on the input. 🔍 How does an analog designer think about this? Lowering the threshold voltage enhances the drive strength, making the transistor act as if it’s a stronger amplifier at low voltages. It’s like adding a gain boost to your amplifier without increasing power! The body terminal, often ignored in digital circuits, becomes an active participant, much like in body-biased analog amplifiers used for low-power operation. In essence, the DTMOS inverter doesn’t just switch—it evolves with the input, making it a natural fit for ultra-low-power circuits where every nanoamp matters. 💡 What’s the Takeaway? 🔹 A CMOS inverter is more than just a switch—it’s a logic-stage amplifier in disguise! 🔹 The DTMOS inverter is an analog-inspired improvement, dynamically enhancing transistor behavior just like body-biased amplifiers. 🔹 Lower nodes demand smarter design choices—when voltage scaling limits traditional inverters, DTMOS steps in as an elegant, analog-aware solution. So next time you see a digital circuit, ask yourself—what’s the hidden analog intuition behind it? That’s the beauty of merging both worlds! 🚀

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Found a fantastic quick-reference guide for Analog Electronics! Whether you are prepping for DIY project or designing a new PCB, having a consolidated resource for BJT biasing, MOSFET small-signal analysis, and Op-Amp configurations is incredibly useful. I’m planning to use this guide to experiment with some practical analog circuits in the lab this week. Specifically, I want to test the limits of the feedback amplifier concepts outlined here against real components. It’s a great refresher for anyone looking to brush up on their analog fundamentals. #Electronics #EngineeringResources #AnalogDesign #OpAmps #DIY #LearningByDoing

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