WikiChip

@WikiChip

The official WikiChip Twitter account. Hardware (logic), computer architectures, & semiconductor engineering. Technical.

New York, NY
en.wikichip.org
Joined November 2016
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  1. Apr 30

    Intel launches 10th Generation Core desktop processors, formerly code name Comet Lake. The new lineup brings 22 new chips with up to 10 cores and 20 threads with turbo frequencies of up to 5.3 GHz.

    7 retweets 27 likes
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  2. Apr 17

    TSMC ramps its 5-nanometer node with good yield and discloses key 3-nanometer (N3) details. N3 will be a full node jump over N5 and is expected to offer over a quarter-billion transistors per each mm² of silicon. More details:

    3 replies 61 retweets 143 likes
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  3. Apr 11

    Ranovus launches its Odin Platform: multi-wavelength Quantum Dot Laser (QDL) silicon photonic engine - 800Gbps to 3.2Tbps single-chip engine as well as co-packaged optics scaling up to 51.2Tbps for next-gen DC switches and other HPC apps.

    16 retweets 58 likes
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  4. Apr 5

    A look at Lakefield: Intel's new mobile-class heterogeneous penta-core SoC. Built using two dies 3D-stacked using Intel's Foveros packaging technology and integrating close to 5 billion transistors, here are the full details:

    4 replies 28 retweets 79 likes
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  5. Mar 21

    TSMC details its 5-nanometer node for mobile and HPC applications. The process features the industry’s highest density transistors with a high-mobility channel and highest-density SRAM cells.

    2 replies 56 retweets 126 likes
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  6. Mar 8

    IBM doubles its 14-nanometer eDRAM density, enabling the packing of hundreds of additional megabytes of cache on the latest z15 microprocessor and system controller.

    2 replies 31 retweets 64 likes
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  7. Mar 3

    TSMC announces an enhancement to its CoWoS packaging technology with support for up to 2x the reticle size. The new technology is ready for next-generation 5-nanometer HPC applications.

    17 retweets 35 likes
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  8. Mar 1

    CEA-Leti demonstrates a high-performance microprocessor architecture with a 96-core MIPS processor built with six chiplets 3D-stacked on an active interposer die.

    20 retweets 46 likes
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  9. Feb 27

    Intel refreshes its second-generation Xeon Scalable lineup mid-cycle with new mainstream dual-socket CPUs, improving performance-per-dollar by as much as 2x over original SKUs.

    4 retweets 15 likes
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  10. Feb 23

    A look at AMD's Radeon RX 5700 GPU built on a 7-nanometer process based on the new Navi microarchitecture and RDNA graphics architecture.

    1 reply 28 retweets 76 likes
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  11. Feb 22

    Last week, Glenn Henry, Centaur co-founder and CHA's NPU architect, presented the NPU design at Stanford's EE380 class. You can watch the talk here:

    2 replies 10 retweets 28 likes
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  12. Feb 22

    Centaur's CHA microarchitecture article has been updated. This is an edge server x86 SoC with eight cores and a 20.5 TOPS integrated NPU.

    1 reply 18 retweets 45 likes
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  13. Feb 21

    The transition to 7 nm greatly enhanced AMD silicon capabilities but introduced new drastic design challenges that required new place and route methodologies and wire engineering.

    2 replies 39 retweets 86 likes
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  14. Feb 10

    Arm launches two new IPs for deeply-embedded AI: the Cortex-M55 with the new M-Profile Vector Extension (Helium), and the Ethos-U55, an ultra-low-power dedicated NPU for embedded applications.

    1 reply 9 retweets 23 likes
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  15. Feb 9

    A dive into the Rosetta ASIC switch, the engine behind Cray's new Slingshot interconnect powering the upcoming Shasta exascale supercomputers.

    1 reply 30 retweets 60 likes
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  16. Feb 6

    Arm's Ethos family takes aim at ubiquitous AI with NPUs for ultra-low power IoT to high-performance smartphones and AR/VR.

    11 retweets 25 likes
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  17. Feb 3

    Just two months after launch, Intel axes Nervana neural processors.

    32 retweets 53 likes
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  18. Jan 24

    A look at Centaur’s new server-class x86 SoC with an integrated neural processor designed for on-chip inference acceleration in the data center.

    1 reply 19 retweets 40 likes
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  19. Jan 22

    ASML saw a strong fourth-quarter in 2019 thanks to a large EUV shipment with the production of NXE:3400C machines ramping up. 26 EUV machines shipped in 2019 with 35 more expected for 2020. Backlog continues to grow.

    10 retweets 22 likes
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  20. Jan 19

    Integrated photonics has long been considered a holy grail for processor communication. Ayar Labs TeraPHY represents a major step forward through the co-packaging of optical I/F with the SoC. First product is an Intel Stratix 10 FPGA with 2 SiPho chiplets.

    1 reply 18 retweets 63 likes
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