Conditional expression in verlog

Question

I want to know how the synthesizer in VIVADO will understand the conditional operator in verlig. An expression like: A = X ? Y : -Y will contain any multiplier since there is the negative sign in the second branch. Does it do first the multiplication of (-1)*Y or it won't use any multiplier at all in hardware.

Regards, Jet

Qiu · Accepted Answer · 2015-03-21 08:37:57Z

3

No, it won't use any multiplier. You'll get a following structure:

enter image description here

As you can see, only one mux and one adder (to achieve two's complement) are used.

answered Mar 21, 2015 at 8:37

Qiu

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