Hi there! My name is Zeeshan Rafique.

"RTL Design and Verification Engineer"

I am an RTL design and Verification engineer with a strong background in Computer Architecture and Digital Logic Design.

💻 Languages:

• SystemVerilog, Verilog, CHISEL
• Universal Verification Methodology (UVM)
• RISC-V Assembly
• C / C++
• Python, Bash, tcl

🧑‍💻 Skills:

• Functional coverage collection
• Random Instruction Sequence Generation
• Unit level Testing / VIP in UVM
• Reusing existing IPs / integration

🖲️ Tools:

• Xcelium, Questa Sim, Vivado (xsim), Verilator, iCarus Verilog, GTK wave
• Vivado (synthesis and implementation), AWS Cloud FPGA
• Genus, Yosys