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  1. svunit svunit Public

    Forked from svunit/svunit

    SystemVerilog

  2. uvm-core uvm-core Public

    Forked from accellera-official/uvm-core

    SystemVerilog

  3. riscv-dv riscv-dv Public

    Forked from chipsalliance/riscv-dv

    Random instruction generator for RISC-V processor verification

    Python

  4. azadi-verify azadi-verify Public

    Forked from merledu/azadi-verify

    This repository contains tests (in C and assembly both), benchmarks and the test-benches for the verification of Azadi SoC.

    Assembly

  5. ibex ibex Public

    Forked from lowRISC/ibex

    Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.

    SystemVerilog