Flappy Bird game on Sipeed Tang Primer 20K FPGA board.
- Resolution: 640x480 60 FPS
- Double buffered HDMI video output using two 300 Kbit BSRAMs and GOWIN DVI TX IP core
- 64.125 MHz frequency for cpu and gpu modules
- Autoplay switch: game plays itself!
main branch
Logic is splitted between cpu and gpu modules. GPU draws primitives: filled and textured rectangles. CPU sends commands to GPU.
- Open project in GOWIN FPGA DESIGNER.
- Click "Run all".
- Set 1, 2, 3, 4 switches to "on" and 5 switch to "off" on board.
- Open Programmer and click "Program/Configure".
- Connect board to monitor using HDMI.
- Press "S1" button once.
Switch 1 should always be enabled (check Sipeed Wiki).
Remaining switches functions are shown in table below.
| 5 | 4 | 3 | 2 | Description | Buttons |
|---|---|---|---|---|---|
| 0 | 0 | 0 | 1 | Red screen | |
| 0 | 0 | 1 | 0 | Green screen | |
| 0 | 0 | 1 | 1 | Blue screen | |
| 0 | 1 | 0 | 0 | Test pattern 1 (diagonals) | |
| 0 | 1 | 0 | 1 | Test pattern 2 (XOR) | Hold S2 to invert colors |
| 0 | 1 | 1 | 0 | Flappy Bird, autoplay off | Hold S2 to make bird fly up |
| 0 | 1 | 1 | 1 | Flappy Bird, autoplay on | Hold S2 to make bird fly up |
| 1 | 0 | 0 | 0 | Test pattern using framebuffer (XOR) | Hold S2 to invert colors |
| x | x | x | x | Black screen |
Button S0 resets almost all modules.
Button S1 resets only modules that draw pixels to framebuffer and farther, it does not reset framebuffer.
| LED | Description |
|---|---|
| 0 | Reset (S0) |
| 1 | All PLLs are locked |
| 2 | You lose! (bird crashed) |
| 3 | Current GPU state is WORK |
| 4 | CPU-GPU FIFO is full (GPU stuck) |
| 5 | CPU done sending commands for current frame |
There is a high-level game model written in Python to debug game logic.
To launch it make sure that you have pygame installed and run python -m model.
Press SPACE to make bird fly up and A to toggle autoplay (default on).
Testbenches are located in tb folder. To run them install Icarus Verilog and GTKWave and follow instructions in tb/README.
Old single-fsm branch
All logic is implemented using single FSM, which renders pixels to framebuffer. Not a good example of SystemVerilog development. 😅
Licensed under MIT license only.