cocotb: Python-based chip (RTL) verification

OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.

Package manager and build abstraction tool for FPGA/ASIC development

Modular hardware build system

An abstraction library for interfacing EDA tools

Pymtl 3 (Mamba), an open-source Python-based hardware generation, simulation, and verification framework

The next generation of OpenLane, rewritten from scratch with a modular architecture

VHDL/Verilog/SystemC code generator, simulator API written in python/c++

Repurposing existing HDL tools to help writing better code

HDL symbol generator

A version of the HDMI2USB firmware based around LiteX tools produced by @enjoy-digital (based on misoc+migen created by @m-labs)

A configurable and approachable tool for FPGA debugging and rapid prototyping.

Control and status register code generator toolchain

Learn how to build our own RV32I core and use it on FPGA.

Control and Status Register map generator for HDL projects

Create fast and efficient standard cell based adders, multipliers and multiply-adders.

An FPGA microcontroller that natively executes LISP

AutoSVA is a tool to automatically generate formal testbenches for unit-level RTL verification. The goal is to, based on annotations made in the signal declaration section of an RTL module, generate liveness properties so that the module would eventually make forward progress.

SVUT is a simple framework to create Verilog/SystemVerilog unit tests. Just focus on your tests!

CoreIR Symbolic Analyzer