Skip to content
View skudlur's full-sized avatar
🦆
Sitting ducks
🦆
Sitting ducks

Block or report skudlur

Report abuse

Contact GitHub support about this user’s behavior. Learn more about reporting abuse.

Report abuse
skudlur/README.md

Greetings fellow geek 👋

I'm Suhas Kudlur Viswanath and I'm a researcher.

I specialize in:

Developing RTL for accelerators, RISC-V processors, and interconnects.

Improving memory locality and performance for multi-core/multi-socket/multi-unit mobile/server systems.

Building research tooling in Rust.

Pinned Loading

  1. diablo diablo Public

    diablo is an Out-Of-Order 64-bit RISC-V processor.

    HTML 17 4

  2. dma-bsv dma-bsv Public

    Direct Memory Access Controller and Memory Interface

    Bluespec 6

  3. TraceCXL TraceCXL Public

    TraceCXL is a rapid algorithmic prototyping framework for CXL hardware modeling.

    Python

  4. cayde cayde Public

    cayde is 32-bit RISC-V core written in SystemVerilog

    SystemVerilog 8 8

  5. RISCulator RISCulator Public

    RISCulator is a RISC-V emulator.

    Rust 12

  6. rv-decoder rv-decoder Public

    RISC-V Decoder library for Rust

    Rust 3 1