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Xtal hart
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Xtal hart

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@ustclug @FPGAOL-CE

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regymm/README.md

Check out my homepage and Telegram channel !

Personal:

  • C / Python / Assembly / Verilog
  • Vim / Firefox / KiCad
  • Open source FPGA toolchains
  • RISC-V hw design & osdev
  • Interested in SDR / amateur radio

Pinned Loading

  1. GenZ GenZ Public

    The open-source Zynq 7000 BSP generator for openXC7

    C 49 1

  2. quasiSoC quasiSoC Public

    Linux capable RISC-V SoC designed to be readable and useful.

    Verilog 155 11

  3. PYNQSDR PYNQSDR Public

    PYNQ-Z1 + AD936X openwifi capable SDR platform

    120 18

  4. SqueakyBoard SqueakyBoard Public

    My self-designed ZYNQ-7010 4-layer developement board.

    TeX 33 6

  5. ymmcu-ft2232 ymmcu-ft2232 Public

    FT2232HL JTAG & UART Downloader

    20 3

  6. pcie_7x pcie_7x Public

    PCIe Endpoint on Xilinx 7-Series FPGAs with the PCIE_2_1 hard block and GTP transceivers

    Verilog 65 7