Welcome to the Digital Forest!
Embark on a December-long FPGA adventure inspired by Advent of Code, where you’ll tackle five hardware design challenges that progressively grow in complexity. This project blends storytelling with technical exploration, teaching key FPGA concepts through engaging and practical tasks.
The Digital Forest challenge series consists of five tasks. These tasks are designed for FPGA boards and focus on using Hardware Description Laanguages (HDLs). While this project is developed on the RealDigital Urbana Board, you are welcome to use any FPGA board you prefer.
The challenges are time-released throughout December.
- Challenge 1: December 1, 2024
- Challenge 2: December 5, 2024
- Challenge 3: December 11, 2024
- Challenge 4: December 18, 2024
- Challenge 5: December 25, 2024
Each challenge will be unlocked in this repository on the specified date. Stay tuned!
To participate, you’ll need:
- An FPGA development board.
- A hardware description language (HDL) toolchain installed:
- AMD Vivado for Xilinx boards.
- Intel Quartus Prime for Intel boards.
- Basic familiarity with Verilog or VHDL.
While some prior knowledge of HDLs is recommended, the challenges include hints to guide you through.
- Clone the repository
git clone https://github.com/realhjx/DigitalForest.git
- Wait for the first challenge to be unlocked on December 1, 2024, and then
git pull
- Work through each challenge in order
- Challenge 1: Basic FPGA Programming。
- Challenge 2: Finite State Machine Design.
- Challenge 3: Mathematical Computation Using FPGA.
- Challenge 4: Custom CPU Implementation.
- Challenge 5: TBD.
We welcome contributions to make Digital Forest even better! You can:
- Report bugs or compatibility issues with specific FPGA boards.
- Improve the documentation or provide additional resources.
Feel free to open an issue or submit a pull request. Let’s grow the Digital Forest together!