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1. ibex ibex Public

   Forked from lowRISC/ibex

   Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.

   SystemVerilog

2. e200_opensource e200_opensource Public

   Forked from SI-RISCV/e200_opensource

   Deprecated, please go to next generation Ultra-Low Power RISC-V Core https://github.com/riscv-mcu/e203_hbirdv2

   Verilog

3. core_ddr3_controller core_ddr3_controller Public

   Forked from ultraembedded/core_ddr3_controller

   A DDR3 memory controller in Verilog for various FPGAs

   Verilog