Cleanup the merge

CMakeLists.txt

@@ -18,10 +18,10 @@ if(NOT DEFINED LLVM_VERSION_MINOR)
   set(LLVM_VERSION_MINOR 0)
 endif()
 if(NOT DEFINED LLVM_VERSION_PATCH)
-  set(LLVM_VERSION_PATCH 1)
+  set(LLVM_VERSION_PATCH 0)
 endif()
 if(NOT DEFINED LLVM_VERSION_SUFFIX)
-  set(LLVM_VERSION_SUFFIX "")
+  set(LLVM_VERSION_SUFFIX svn)
 endif()
 
 if (NOT PACKAGE_VERSION)

docs/ReleaseNotes.rst

@@ -33,12 +33,12 @@ page <https://llvm.org/releases/>`_.
 
 Non-comprehensive list of changes in this release
 =================================================
-
-* The Windows installer no longer includes a Visual Studio integration.
-  Instead, a new
-  `LLVM Compiler Toolchain Visual Studio extension <https://marketplace.visualstudio.com/items?itemName=LLVMExtensions.llvm-toolchain>`_
-  is available on the Visual Studio Marketplace. The new integration
-  supports Visual Studio 2017.
+.. NOTE
+   For small 1-3 sentence descriptions, just add an entry at the end of
+   this list. If your description won't fit comfortably in one bullet
+   point (e.g. maybe you would like to give an example of the
+   functionality, or simply have a lot to talk about), see the `NOTE` below
+   for adding a new subsection.
 
 * The **llvm-cov** tool can now export lcov trace files using the
   `-format=lcov` option of the `export` command.
@@ -48,162 +48,52 @@ Non-comprehensive list of changes in this release
   functionality.  See `Writing an LLVM Pass
   <WritingAnLLVMPass.html#setting-up-the-build-environment>`_.
 
-* Added support for the ``.rva`` assembler directive for COFF targets.
-
-* The :program:`llvm-rc` tool (Windows Resource Compiler) has been improved
-  a bit. There are still known missing features, but it is generally usable
-  in many cases. (The tool still doesn't preprocess input files automatically,
-  but it can now handle leftover C declarations in preprocessor output, if
-  given output from a preprocessor run externally.)
-
-* CodeView debug info can now be emitted for MinGW configurations, if requested.
-
-* The :program:`opt` tool now supports the ``-load-pass-plugin`` option for
-  loading pass plugins for the new PassManager.
+.. NOTE
+   If you would like to document a larger change, then you can add a
+   subsection about it right here. You can copy the following boilerplate
+   and un-indent it (the indentation causes it to be inside this comment).
 
-* Support for profiling JITed code with perf.
+   Special New Feature
+   -------------------
 
+   Makes programs 10x faster by doing Special New Thing.
 
 Changes to the LLVM IR
 ----------------------
 
 
-Changes to the AArch64 Target
------------------------------
-
-* The ``.inst`` assembler directive is now usable on both COFF and Mach-O
-  targets, in addition to ELF.
-
-* Support for most remaining COFF relocations has been added.
-
-* Support for TLS on Windows has been added.
-
-* Assembler and disassembler support for the ARM Scalable Vector Extension has
-  been added.
-
-Changes to the ARM Target
--------------------------
-
-* The ``.inst`` assembler directive is now usable on both COFF and Mach-O
-  targets, in addition to ELF. For Thumb, it can now also automatically
-  deduce the instruction size, without having to specify it with
-  e.g. ``.inst.w`` as before.
-
-Changes to the Hexagon Target
------------------------------
+Changes to the ARM Backend
+--------------------------
 
-* Hexagon now supports auto-vectorization for HVX. It is disabled by default
-  and can be turned on with ``-fvectorize``. For auto-vectorization to take
-  effect, code generation for HVX needs to be enabled with ``-mhvx``.
-  The complete set of options should include ``-fvectorize``, ``-mhvx``,
-  and ``-mhvx-length={64b|128b}``.
+ During this release ...
 
-* The support for Hexagon ISA V4 is deprecated and will be removed in the
-  next release.
 
 Changes to the MIPS Target
 --------------------------
 
-During this release the MIPS target has:
-
-* Added support for Virtualization, Global INValidate ASE,
-  and CRC ASE instructions.
-
-* Introduced definitions of ``[d]rem``, ``[d]remu``,
-  and microMIPSR6 ``ll/sc`` instructions.
-
-* Shrink-wrapping is now supported and enabled by default (except for ``-O0``).
-
-* Extended size reduction pass by the LWP and SWP instructions.
-
-* Gained initial support of GlobalISel instruction selection framework.
-
-* Updated the P5600 scheduler model not to use instruction itineraries.
-
-* Added disassembly support for comparison and fused (negative) multiply
-  ``add/sub`` instructions.
-
-* Improved the selection of multiple instructions.
-
-* Load/store ``lb``, ``sb``, ``ld``, ``sd``, ``lld``, ... instructions
-  now support 32/64-bit offsets.
-
-* Added support for ``y``, ``M``, and ``L`` inline assembler operand codes.
-
-* Extended list of relocations supported by the ``.reloc`` directive
-
-* Fixed using a wrong register class for creating an emergency
-  spill slot for mips3 / n64 ABI.
+ During this release ...
 
-* MIPS relocation types were generated for microMIPS code.
-
-* Corrected definitions of multiple instructions (``lwp``, ``swp``, ``ctc2``,
-  ``cfc2``, ``sync``, ``synci``, ``cvt.d.w``, ...).
-
-* Fixed atomic operations at ``-O0`` level.
-
-* Fixed local dynamic TLS with Sym64
 
 Changes to the PowerPC Target
 -----------------------------
 
-During this release the PowerPC target has:
+ During this release ...
 
-* Replaced the list scheduler for post register allocation with the machine scheduler.
+Changes to the X86 Target
+-------------------------
 
 * Machine model for AMD bdver2 (Piledriver) CPU was added. It is used to support
   instruction scheduling and other instruction cost heuristics.
 
-* Added support for ``symbol@high`` and ``symbol@higha`` symbol modifiers.
-
-* Added support for quad-precision floating point type (``__float128``) under the llvm option ``-enable-ppc-quad-precision``.
-
-* Added dump function to ``LatencyPriorityQueue``.
-
-* Completed the Power9 scheduler model.
-
-* Optimized TLS code generation.
-
-* Improved MachineLICM for hoisting constant stores.
-
-* Improved code generation to reduce register use by using more register + immediate instructions.
-
-* Improved code generation to better exploit rotate-and-mask instructions.
-
-* Fixed the bug in dynamic loader for JIT which crashed NNVM.
-
-* Numerous bug fixes and code cleanups.
-
-Changes to the SystemZ Target
+Changes to the AMDGPU Target
 -----------------------------
 
-During this release the SystemZ target has:
-
-* Added support for vector registers in inline asm statements.
-
-* Added support for stackmaps, patchpoints, and the anyregcc
-  calling convention.
-
-* Changed the default function alignment to 16 bytes.
-
-* Improved codegen for condition code handling.
-
-* Improved instruction scheduling and microarchitecture tuning for z13/z14.
+ During this release ...
 
-* Fixed support for generating GCOV coverage data.
-
-* Fixed some codegen bugs.
-
-Changes to the X86 Target
--------------------------
+Changes to the AVR Target
+-----------------------------
 
-* The calling convention for the ``f80`` data type on MinGW targets has been
-  fixed. Normally, the calling convention for this type is handled within clang,
-  but if an intrinsic is used, which LLVM expands into a libcall, the
-  proper calling convention needs to be supported in LLVM as well. (Note,
-  on Windows, this data type is only used for long doubles in MinGW
-  environments - in MSVC environments, long doubles are the same size as
-  normal doubles.)
+ During this release ...
 
 Changes to the OCaml bindings
 -----------------------------
@@ -214,26 +104,13 @@ Changes to the C API
 --------------------
 
 
-* Expanded the OrcJIT APIs so they can register event listeners like debuggers
-  and profilers.
-
 Changes to the DAG infrastructure
 ---------------------------------
 
 External Open Source Projects Using LLVM 8
 ==========================================
 
-Zig Programming Language
-------------------------
-
-`Zig <https://ziglang.org>`_  is an open-source programming language designed
-for robustness, optimality, and clarity. Zig is an alternative to C, providing
-high level features such as generics, compile time function execution, partial
-evaluation, and LLVM-based coroutines, while exposing low level LLVM IR
-features such as aliases and intrinsics. Zig uses Clang to provide automatic
-import of .h symbols - even inline functions and macros. Zig uses LLD combined
-with lazily building compiler-rt to provide out-of-the-box cross-compiling for
-all supported targets.
+* A project...
 
 
 Additional Information

docs/index.rst

@@ -1,6 +1,11 @@
 Overview
 ========
 
+.. warning::
+
+   If you are using a released version of LLVM, see `the download page
+   <http://llvm.org/releases/>`_ to find your documentation.
+
 The LLVM compiler infrastructure supports a wide range of projects, from
 industrial strength compilers to specialized JIT applications to small
 research projects.

lib/Target/AArch64/AArch64SystemOperands.td

@@ -1460,15 +1460,6 @@ def : RWSysReg<"TFSR_EL12",        0b11, 0b101, 0b0110, 0b0110, 0b000>;
 def : RWSysReg<"TFSRE0_EL1",       0b11, 0b000, 0b0110, 0b0110, 0b001>;
 } // HasMTE
 
-// SVE control registers
-//                                 Op0   Op1    CRn     CRm     Op2
-let Requires = [{ {AArch64::FeatureSVE} }] in {
-def : RWSysReg<"ZCR_EL1",          0b11, 0b000, 0b0001, 0b0010, 0b000>;
-def : RWSysReg<"ZCR_EL2",          0b11, 0b100, 0b0001, 0b0010, 0b000>;
-def : RWSysReg<"ZCR_EL3",          0b11, 0b110, 0b0001, 0b0010, 0b000>;
-def : RWSysReg<"ZCR_EL12",         0b11, 0b101, 0b0001, 0b0010, 0b000>;
-}
-
 // Cyclone specific system registers
 //                                 Op0    Op1     CRn     CRm    Op2
 let Requires = [{ {AArch64::ProcCyclone} }] in

test/CodeGen/X86/known-signbits-vector.ll

@@ -323,24 +323,7 @@ define <4 x float> @signbits_ashr_sext_select_shuffle_sitofp(<4 x i64> %a0, <4 x
 ; X32-NEXT:    movl %esp, %ebp
 ; X32-NEXT:    andl $-16, %esp
 ; X32-NEXT:    subl $16, %esp
-; X32-NEXT:    vmovdqa {{.*#+}} xmm3 = [33,0,63,0]
-; X32-NEXT:    vmovdqa {{.*#+}} xmm4 = [0,2147483648,0,2147483648]
-; X32-NEXT:    vpsrlq %xmm3, %xmm4, %xmm5
-; X32-NEXT:    vpshufd {{.*#+}} xmm6 = xmm3[2,3,0,1]
-; X32-NEXT:    vpsrlq %xmm6, %xmm4, %xmm4
-; X32-NEXT:    vpblendw {{.*#+}} xmm4 = xmm5[0,1,2,3],xmm4[4,5,6,7]
-; X32-NEXT:    vextractf128 $1, %ymm2, %xmm5
-; X32-NEXT:    vpsrlq %xmm6, %xmm5, %xmm7
-; X32-NEXT:    vpsrlq %xmm3, %xmm5, %xmm5
-; X32-NEXT:    vpblendw {{.*#+}} xmm5 = xmm5[0,1,2,3],xmm7[4,5,6,7]
-; X32-NEXT:    vpsrlq %xmm6, %xmm2, %xmm6
-; X32-NEXT:    vpsrlq %xmm3, %xmm2, %xmm2
-; X32-NEXT:    vpblendw {{.*#+}} xmm2 = xmm2[0,1,2,3],xmm6[4,5,6,7]
 ; X32-NEXT:    vpmovsxdq 16(%ebp), %xmm3
-; X32-NEXT:    vpxor %xmm4, %xmm5, %xmm5
-; X32-NEXT:    vpsubq %xmm4, %xmm5, %xmm5
-; X32-NEXT:    vpxor %xmm4, %xmm2, %xmm2
-; X32-NEXT:    vpsubq %xmm4, %xmm2, %xmm2
 ; X32-NEXT:    vpmovsxdq 8(%ebp), %xmm4
 ; X32-NEXT:    vextractf128 $1, %ymm2, %xmm5
 ; X32-NEXT:    vpsrlq $33, %xmm5, %xmm5