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  1. rtl_basics rtl_basics Public

    Refreshing basics for writing RTL and Testbench in Verilog

    SystemVerilog 1

  2. ESP8266 ESP8266 Public

  3. SmartPot SmartPot Public

    Smart Flower Pot

  4. Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA Public

    Forked from ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA

    Verilog Generator of Neural Net Digit Detector for FPGA

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  5. sobel sobel Public

    Forked from usmanwardag/sobel

    Implementation of Sobel Filter in Verilog

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  6. utp-cve2 utp-cve2 Public

    Forked from openhwgroup/cve2

    Ibex is a small 32 bit RISC-V CPU core (RV32IMC/EMC) with a two stage pipeline, previously known as zero-riscy.

    SystemVerilog