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  1. ibex ibex Public

    Forked from lowRISC/ibex

    Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.

    SystemVerilog

  2. chipyard chipyard Public

    Forked from ucb-bar/chipyard

    An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more

    Scala

  3. rv321 rv321 Public

  4. TXR_Training TXR_Training Public

    VLSI Training

    Verilog 1